2 * Copyright (C) 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
29 /*-----------------------------------------------------------------------
30 * User configurable settings:
32 * CONFIG_IPADDR_LS - the IP address of the LinkStation
33 * CONFIG_SERVERIP_LS - the address of the server for NFS/TFTP/DHCP/BOOTP
35 * CONFIG_NCIP_LS - the adress of the computer running net console
36 * if not configured, it will be set to
41 #define CONFIG_IPADDR_LS 192.168.11.150
42 #define CONFIG_SERVERIP_LS 192.168.11.149
44 #if !defined(CONFIG_IPADDR_LS) || !defined(CONFIG_SERVERIP_LS)
45 #error Both CONFIG_IPADDR_LS and CONFIG_SERVERIP_LS must be defined
48 #if !defined(CONFIG_NCIP_LS)
49 #define CONFIG_NCIP_LS CONFIG_SERVERIP_LS
52 /*----------------------------------------------------------------------
53 * DO NOT CHANGE ANYTHING BELOW, UNLESS YOU KNOW WHAT YOU ARE DOING
54 *---------------------------------------------------------------------*/
56 #define CONFIG_MPC8245 1
57 #define CONFIG_LINKSTATION 1
59 /*---------------------------------------
62 * LinkStation HDLAN /KuroBox Standard (CONFIG_HLAN)
63 * LinkStation old model (CONFIG_LAN) - totally untested
64 * LinkStation HGLAN / KuroBox HG (CONFIG_HGLAN)
66 * Models not supported yet
67 * TeraStatin (CONFIG_HTGL)
70 #if defined(CONFIG_HLAN) || defined(CONFIG_LAN)
71 #define CONFIG_IDENT_STRING " LinkStation / KuroBox"
72 #elif defined(CONFIG_HGLAN)
73 #define CONFIG_IDENT_STRING " LinkStation HG / KuroBox HG"
74 #elif defined(CONFIG_HTGL)
75 #define CONFIG_IDENT_STRING " TeraStation"
77 #error No LinkStation model defined
80 #define CONFIG_BOOTDELAY 5
81 #define CONFIG_ZERO_BOOTDELAY_CHECK
82 #undef CONFIG_BOOT_RETRY_TIME
84 #define CONFIG_AUTOBOOT_KEYED
85 #define CONFIG_AUTOBOOT_PROMPT "Boot in %02d seconds ('s' to stop)..."
86 #define CONFIG_AUTOBOOT_STOP_STR "s"
88 #define CONFIG_CMD_IDE
89 #define CONFIG_CMD_PCI
90 #define CONFIG_CMD_DHCP
91 #define CONFIG_CMD_PING
92 #define CONFIG_CMD_EXT2
94 #define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
96 #define CONFIG_OF_LIBFDT 1
98 #define OF_CPU "PowerPC,603e"
99 #define OF_SOC "soc10x@80000000"
100 #define OF_STDOUT_PATH "/soc10x/serial@80004600"
102 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
103 #include <config_cmd_default.h>
106 * Miscellaneous configurable options
108 #define CFG_LONGHELP /* undef to save memory */
109 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
110 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
112 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
113 #define CFG_MAXARGS 16 /* Max number of command args */
114 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
115 #define CFG_LOAD_ADDR 0x00800000 /* Default load address: 8 MB */
117 #define CONFIG_BOOTCOMMAND "run bootcmd1"
118 #define CONFIG_BOOTARGS "root=/dev/sda1 console=ttyS1,57600 netconsole=@192.168.1.7/eth0,@192.168.1.1/00:50:BF:A4:59:71 rtc-rs5c372.probe=0,0x32 debug"
119 #define CONFIG_NFSBOOTCOMMAND "bootp;run nfsargs;bootm"
121 #define CFG_CONSOLE_IS_IN_ENV
123 #define XMK_STR(x) #x
124 #define MK_STR(x) XMK_STR(x)
126 #if defined(CONFIG_HLAN) || defined(CONFIG_LAN)
127 #define UBFILE "share/u-boot/u-boot-hd.flash.bin"
128 #elif defined(CONFIG_HGLAN)
129 #define UBFILE "share/u-boot/u-boot-hg.flash.bin"
130 #elif defined(CONFIG_HTGL)
131 #define UBFILE "share/u-boot/u-boot-ht.flash.bin"
133 #error No LinkStation model defined
136 #define CONFIG_EXTRA_ENV_SETTINGS \
141 "ipaddr="MK_STR(CONFIG_IPADDR_LS)"\0" \
142 "netmask=255.255.255.0\0" \
143 "serverip="MK_STR(CONFIG_SERVERIP_LS)"\0" \
144 "ncip="MK_STR(CONFIG_NCIP_LS)"\0" \
146 "nc=setenv stdin nc;setenv stdout nc;setenv stderr nc\0" \
147 "ser=setenv stdin serial;setenv stdout serial;setenv stderr serial\0" \
150 "hdfile=boot/uImage\0" \
151 "hdload=echo Loading ${hdpart}:${hdfile};ext2load ide ${hdpart} ${ldaddr} ${hdfile};ext2load ide ${hdpart} 7f0000 boot/kuroboxHG.dtb\0" \
152 "boothd=setenv bootargs " CONFIG_BOOTARGS ";bootm ${ldaddr} - 7f0000\0" \
153 "hdboot=run hdload;run boothd\0" \
154 "flboot=setenv bootargs root=/dev/hda1;bootm ffc00000\0" \
155 "emboot=setenv bootargs root=/dev/ram0;bootm ffc00000\0" \
156 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
157 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
159 "bootcmd1=run hdboot;run flboot\0" \
160 "bootcmd2=run flboot\0" \
161 "bootcmd3=run emboot\0" \
162 "writeng=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4e474e47 1;cp.b 800000 fff70000 4\0" \
163 "writeok=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4f4b4f4b 1;cp.b 800000 fff70000 4\0" \
165 "ubfile="UBFILE"\0" \
166 "ubload=echo Loading ${ubpart}:${ubfile};ext2load ide ${ubpart} ${ldaddr} ${ubfile}\0" \
167 "ubsaddr=fff00000\0" \
168 "ubeaddr=fff2ffff\0" \
169 "ubflash=protect off ${ubsaddr} ${ubeaddr};era ${ubsaddr} ${ubeaddr};cp.b ${ldaddr} ${ubsaddr} ${filesize};cmp.b ${ldaddr} ${ubsaddr} ${filesize}\0" \
170 "upgrade=run ubload ubflash\0"
172 /*-----------------------------------------------------------------------
176 /* Verified: CONFIG_PCI_PNP doesn't work */
177 #undef CONFIG_PCI_PNP
178 #define CONFIG_PCI_SCAN_SHOW
180 #ifndef CONFIG_PCI_PNP
181 /* Keep the following defines in sync with the BAT mappings */
183 #define PCI_ETH_IOADDR 0xbfff00
184 #define PCI_ETH_MEMADDR 0xbffffc00
185 #define PCI_IDE_IOADDR 0xbffed0
186 #define PCI_IDE_MEMADDR 0xbffffb00
187 #define PCI_USB0_IOADDR 0
188 #define PCI_USB0_MEMADDR 0xbfffe000
189 #define PCI_USB1_IOADDR 0
190 #define PCI_USB1_MEMADDR 0xbfffd000
191 #define PCI_USB2_IOADDR 0
192 #define PCI_USB2_MEMADDR 0xbfffcf00
196 /*-----------------------------------------------------------------------
199 #define CONFIG_NET_MULTI
201 #if defined(CONFIG_LAN) || defined(CONFIG_HLAN)
203 #define CONFIG_TULIP_USE_IO
204 #elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
205 #define CONFIG_RTL8169
208 #define CONFIG_NET_RETRY_COUNT 5
210 #define CONFIG_NETCONSOLE
212 /*-----------------------------------------------------------------------
213 * Start addresses for the final memory configuration
214 * (Set up by the startup code)
215 * Please note that CFG_SDRAM_BASE _must_ start at 0
217 #define CFG_SDRAM_BASE 0x00000000
219 #define CFG_FLASH_BASE 0xFFC00000
220 #define CFG_FLASH_SIZE 0x00400000
221 #define CFG_MONITOR_BASE TEXT_BASE
223 #define CFG_RESET_ADDRESS 0xFFF00100
224 #define CFG_EUMB_ADDR 0x80000000
225 #define CFG_PCI_MEM_ADDR 0xB0000000
226 #define CFG_MISC_REGION_ADDR 0xFE000000
228 #define CFG_MONITOR_LEN 0x00040000 /* 256 kB */
229 #define CFG_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */
231 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
232 #define CFG_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */
234 /* Maximum amount of RAM */
235 #if defined(CONFIG_HLAN) || defined(CONFIG_LAN)
236 #define CFG_MAX_RAM_SIZE 0x04000000 /* 64MB of SDRAM */
237 #elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
238 #define CFG_MAX_RAM_SIZE 0x08000000 /* 128MB of SDRAM */
240 #error Unknown LinkStation type
243 /*-----------------------------------------------------------------------
244 * Change TEXT_BASE in bord/linkstation/config.mk to get a RAM build
246 * RAM based builds are for testing purposes. A Linux module, uloader.o,
247 * exists to load U-Boot and pass control to it
249 * Always do "make clean" after changing the build type
251 #if CFG_MONITOR_BASE < CFG_FLASH_BASE
255 /*-----------------------------------------------------------------------
256 * Definitions for initial stack pointer and data area
258 #if 1 /* RAM is available when the first C function is called */
259 #define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE - 0x1000)
261 #define CFG_INIT_RAM_ADDR 0x40000000
263 #define CFG_INIT_RAM_END 0x1000
264 #define CFG_GBL_DATA_SIZE 128
265 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
267 /*----------------------------------------------------------------------
268 * Serial configuration
270 #define CONFIG_CONS_INDEX 1
271 #define CONFIG_BAUDRATE 57600
272 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
275 #define CFG_NS16550_SERIAL
277 #define CFG_NS16550_REG_SIZE 1
279 #define CFG_NS16550_CLK get_bus_freq(0)
281 #define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4600) /* Console port */
282 #define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4500) /* AVR port */
285 * Low Level Configuration Settings
286 * (address mappings, register initial values, etc.)
287 * You should know what you are doing if you make changes here.
288 * For the detail description refer to the MPC8245 user's manual.
290 * Unless indicated otherwise, the values are
291 * taken from the orignal Linkstation boot code
293 * Most of the low level configuration setttings are normally used
294 * in cpu/mpc824x/cpu_init.c which is NOT used by this implementation.
295 * Low level initialisation is done in board/linkstation/early_init.S
296 * The values below are included for reference purpose only
299 /* FIXME: 32.768 MHz is the crystal frequency but */
300 /* the real frequency is lower by about 0.75% */
301 #define CONFIG_SYS_CLK_FREQ 32768000
304 /* Bit-field values for MCCR1. */
306 #define CFG_ROMFAL 11
308 #define CFG_BANK0_ROW 2 /* Only bank 0 used: 13 x n x 4 */
309 #define CFG_BANK1_ROW 0
310 #define CFG_BANK2_ROW 0
311 #define CFG_BANK3_ROW 0
312 #define CFG_BANK4_ROW 0
313 #define CFG_BANK5_ROW 0
314 #define CFG_BANK6_ROW 0
315 #define CFG_BANK7_ROW 0
317 /* Bit-field values for MCCR2. */
319 #if defined(CONFIG_LAN) || defined(CONFIG_HLAN)
320 #define CFG_REFINT 0x15e0
321 #elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
322 #define CFG_REFINT 0x1580
325 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
326 #define CFG_BSTOPRE 0x91c
328 /* Bit-field values for MCCR3. */
331 /* Bit-field values for MCCR4. */
332 #define CFG_PRETOACT 2
333 #define CFG_ACTTOPRE 2 /* Original value was 2 */
335 #if defined(CONFIG_LAN) || defined(CONFIG_HLAN)
336 #define CFG_SDMODE_CAS_LAT 2 /* For 100MHz bus */
337 /*#define CFG_SDMODE_BURSTLEN 3*/
338 #elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
339 #define CFG_SDMODE_CAS_LAT 3 /* For 133MHz bus */
340 /*#define CFG_SDMODE_BURSTLEN 2*/
342 #define CFG_REGISTERD_TYPE_BUFFER 1
343 #define CFG_EXTROM 1 /* Original setting but there is no EXTROM */
344 #define CFG_REGDIMM 0
345 #define CFG_DBUS_SIZE2 1
346 #define CFG_SDMODE_WRAP 0
348 #define CFG_PGMAX 0x32 /* All boards use this setting. Original 0x92 */
349 #define CFG_SDRAM_DSCD 0x30
351 /* Memory bank settings.
352 * Only bits 20-29 are actually used from these vales to set the
353 * start/end addresses. The upper two bits will always be 0, and the lower
354 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
355 * address. Refer to the MPC8240 book.
358 #define CFG_BANK0_START 0x00000000
359 #define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
360 #define CFG_BANK0_ENABLE 1
361 #define CFG_BANK1_START 0x3ff00000
362 #define CFG_BANK1_END 0x3fffffff
363 #define CFG_BANK1_ENABLE 0
364 #define CFG_BANK2_START 0x3ff00000
365 #define CFG_BANK2_END 0x3fffffff
366 #define CFG_BANK2_ENABLE 0
367 #define CFG_BANK3_START 0x3ff00000
368 #define CFG_BANK3_END 0x3fffffff
369 #define CFG_BANK3_ENABLE 0
370 #define CFG_BANK4_START 0x3ff00000
371 #define CFG_BANK4_END 0x3fffffff
372 #define CFG_BANK4_ENABLE 0
373 #define CFG_BANK5_START 0x3ff00000
374 #define CFG_BANK5_END 0x3fffffff
375 #define CFG_BANK5_ENABLE 0
376 #define CFG_BANK6_START 0x3ff00000
377 #define CFG_BANK6_END 0x3fffffff
378 #define CFG_BANK6_ENABLE 0
379 #define CFG_BANK7_START 0x3ff00000
380 #define CFG_BANK7_END 0x3fffffff
381 #define CFG_BANK7_ENABLE 0
383 #define CFG_ODCR 0x15
385 /*----------------------------------------------------------------------
386 * Initial BAT mappings
390 * 1) GUARDED and WRITETHROUGH not allowed in IBATS
391 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
395 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
396 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
398 #define CFG_DBAT0L CFG_IBAT0L
399 #define CFG_DBAT0U CFG_IBAT0U
401 /* EUMB: 1MB of address space */
402 #define CFG_IBAT1L (CFG_EUMB_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
403 #define CFG_IBAT1U (CFG_EUMB_ADDR | BATU_BL_1M | BATU_VS | BATU_VP)
405 #define CFG_DBAT1L (CFG_IBAT1L | BATL_GUARDEDSTORAGE)
406 #define CFG_DBAT1U CFG_IBAT1U
408 /* PCI Mem: 256MB of address space */
409 #define CFG_IBAT2L (CFG_PCI_MEM_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
410 #define CFG_IBAT2U (CFG_PCI_MEM_ADDR | BATU_BL_256M | BATU_VS | BATU_VP)
412 #define CFG_DBAT2L (CFG_IBAT2L | BATL_GUARDEDSTORAGE)
413 #define CFG_DBAT2U CFG_IBAT2U
415 /* PCI and local ROM/Flash: last 32MB of address space */
416 #define CFG_IBAT3L (CFG_MISC_REGION_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
417 #define CFG_IBAT3U (CFG_MISC_REGION_ADDR | BATU_BL_32M | BATU_VS | BATU_VP)
419 #define CFG_DBAT3L (CFG_IBAT3L | BATL_GUARDEDSTORAGE)
420 #define CFG_DBAT3U CFG_IBAT3U
423 * For booting Linux, the board info and command line data
424 * have to be in the first 8 MB of memory, since this is
425 * the maximum mapped by the Linux kernel during initialization.
427 * FIXME: This doesn't appear to be true for the newer kernels
428 * which map more that 8 MB
430 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
432 /*-----------------------------------------------------------------------
435 #define CFG_FLASH_CFI /* The flash is CFI compatible */
436 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
438 #undef CFG_FLASH_PROTECTION
439 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
440 #define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
441 #define CFG_MAX_FLASH_SECT 72 /* Max number of sectors per flash */
443 #define CFG_FLASH_ERASE_TOUT 12000
444 #define CFG_FLASH_WRITE_TOUT 1000
446 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
448 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
449 #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
451 #define CFG_ENV_IS_IN_FLASH
453 * The original LinkStation flash organisation uses
454 * 448 kB (0xFFF00000 - 0xFFF6FFFF) for the boot loader
455 * We use the last sector of this area to store the environment
456 * which leaves max. 384 kB for the U-Boot itself
458 #define CFG_ENV_ADDR 0xFFF60000
459 #define CFG_ENV_SIZE 0x00010000
460 #define CFG_ENV_SECT_SIZE 0x00010000
462 /*-----------------------------------------------------------------------
463 * Cache Configuration
465 #define CFG_CACHELINE_SIZE 32
466 #ifdef CONFIG_CMD_KGDB
467 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
470 /*-----------------------------------------------------------------------
471 * IDE/ATA definitions
473 #undef CONFIG_IDE_LED /* No IDE LED */
474 #define CONFIG_IDE_RESET /* no reset for ide supported */
475 #define CONFIG_IDE_PREINIT /* check for units */
476 #define CONFIG_LBA48 /* 48 bit LBA supported */
478 #if defined(CONFIG_LAN) || defined(CONFIG_HLAN) || defined(CONFIG_HGLAN)
479 #define CFG_IDE_MAXBUS 1 /* Scan only 1 IDE bus */
480 #define CFG_IDE_MAXDEVICE 1 /* Only 1 drive per IDE bus */
481 #elif defined(CONFIG_HGTL)
482 #define CFG_IDE_MAXBUS 2 /* Max. 2 IDE busses */
483 #define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
485 #error Config IDE: Unknown LinkStation type
488 #define CFG_ATA_BASE_ADDR 0
490 #define CFG_ATA_DATA_OFFSET 0 /* Offset for data I/O */
491 #define CFG_ATA_REG_OFFSET 0 /* Offset for normal registers */
492 #define CFG_ATA_ALT_OFFSET 0 /* Offset for alternate registers */
494 /*-----------------------------------------------------------------------
495 * Partitions and file system
497 #define CONFIG_DOS_PARTITION
499 /*-----------------------------------------------------------------------
500 * Internal Definitions
504 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
505 #define BOOTFLAG_WARM 0x02 /* Software reboot */
507 #endif /* __CONFIG_H */