3 * Sangmoon Kim, dogoil@etinsys.com.
5 * SPDX-License-Identifier: GPL-2.0+
11 #define CONFIG_MPC8245 1
12 #define CONFIG_KVME080 1
14 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
16 #define CONFIG_CONS_INDEX 1
18 #define CONFIG_BAUDRATE 115200
20 #define CONFIG_BOOTDELAY 5
22 #define CONFIG_IPADDR 192.168.0.2
23 #define CONFIG_NETMASK 255.255.255.0
24 #define CONFIG_SERVERIP 192.168.0.1
26 #define CONFIG_BOOTARGS \
27 "console=ttyS0,115200 " \
28 "root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \
29 "ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \
30 "kvme080:eth0:none " \
31 "mtdparts=phys_mapped_flash:12m(root),-(kernel)"
33 #define CONFIG_BOOTCOMMAND \
34 "tftp 800000 kvme080/uImage; " \
37 #define CONFIG_LOADADDR 800000
39 #define CONFIG_BOARD_EARLY_INIT_F
40 #define CONFIG_BOARD_EARLY_INIT_R
41 #define CONFIG_MISC_INIT_R
43 #define CONFIG_LOADS_ECHO 1
44 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
46 #undef CONFIG_WATCHDOG
51 #define CONFIG_BOOTP_SUBNETMASK
52 #define CONFIG_BOOTP_GATEWAY
53 #define CONFIG_BOOTP_HOSTNAME
54 #define CONFIG_BOOTP_BOOTPATH
55 #define CONFIG_BOOTP_BOOTFILESIZE
58 #define CONFIG_MAC_PARTITION
59 #define CONFIG_DOS_PARTITION
61 #define CONFIG_RTC_DS164x
65 * Command line configuration.
67 #include <config_cmd_default.h>
69 #define CONFIG_CMD_ASKENV
70 #define CONFIG_CMD_CACHE
71 #define CONFIG_CMD_DATE
72 #define CONFIG_CMD_DHCP
73 #define CONFIG_CMD_DIAG
74 #define CONFIG_CMD_EEPROM
75 #define CONFIG_CMD_ELF
76 #define CONFIG_CMD_I2C
77 #define CONFIG_CMD_JFFS2
78 #define CONFIG_CMD_NFS
79 #define CONFIG_CMD_PCI
80 #define CONFIG_CMD_PING
81 #define CONFIG_CMD_SDRAM
82 #define CONFIG_CMD_SNTP
85 #define CONFIG_NETCONSOLE
87 #define CONFIG_SYS_LONGHELP
88 #define CONFIG_SYS_CBSIZE 256
89 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
90 #define CONFIG_SYS_MAXARGS 16
91 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
93 #define CONFIG_SYS_MEMTEST_START 0x00400000
94 #define CONFIG_SYS_MEMTEST_END 0x07C00000
96 #define CONFIG_SYS_LOAD_ADDR 0x00100000
98 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
99 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
100 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
102 #define CONFIG_SYS_SDRAM_BASE 0x00000000
103 #define CONFIG_SYS_FLASH_BASE 0x7C000000
104 #define CONFIG_SYS_EUMB_ADDR 0xFC000000
105 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xFF000000
106 #define CONFIG_SYS_NS16550_COM1 0xFF080000
107 #define CONFIG_SYS_NS16550_COM2 0xFF080010
108 #define CONFIG_SYS_NS16550_COM3 0xFF080020
109 #define CONFIG_SYS_NS16550_COM4 0xFF080030
110 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
112 #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
113 #define CONFIG_SYS_FLASH_SIZE (16 * 1024 * 1024)
114 #define CONFIG_SYS_NVRAM_SIZE 0x7FFF8
116 #define CONFIG_VERY_BIG_RAM
118 #define CONFIG_SYS_MONITOR_LEN 0x00040000
119 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
120 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
122 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
124 #define CONFIG_SYS_FLASH_CFI
125 #define CONFIG_FLASH_CFI_DRIVER
126 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
127 #define CONFIG_SYS_FLASH_PROTECTION
128 #define CONFIG_SYS_FLASH_EMPTY_INFO
129 #define CONFIG_SYS_FLASH_PROTECT_CLEAR
131 #define CONFIG_SYS_MAX_FLASH_BANKS 1
132 #define CONFIG_SYS_MAX_FLASH_SECT 256
134 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000
135 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
137 #define CONFIG_SYS_JFFS2_FIRST_BANK 0
138 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
140 #define CONFIG_ENV_IS_IN_NVRAM 1
141 #define CONFIG_ENV_OVERWRITE 1
142 #define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
143 #define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
144 #define CONFIG_ENV_SIZE 0x400
145 #define CONFIG_ENV_OFFSET 0
147 #define CONFIG_SYS_NS16550
148 #define CONFIG_SYS_NS16550_SERIAL
149 #define CONFIG_SYS_NS16550_REG_SIZE 1
150 #define CONFIG_SYS_NS16550_CLK 14745600
153 #define CONFIG_PCI_INDIRECT_BRIDGE
154 #define CONFIG_PCI_PNP
156 #define CONFIG_EEPRO100
157 #define CONFIG_EEPRO100_SROM_WRITE
159 #define CONFIG_SYS_RX_ETH_BUFFER 8
161 #define CONFIG_HARD_I2C 1
162 #define CONFIG_SYS_I2C_SPEED 400000
163 #define CONFIG_SYS_I2C_SLAVE 0x7F
165 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
166 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
167 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
168 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
170 #define CONFIG_SYS_CLK_FREQ 33333333
172 #define CONFIG_SYS_CACHELINE_SIZE 32
173 #if defined(CONFIG_CMD_KGDB)
174 # define CONFIG_SYS_CACHELINE_SHIFT 5
177 #define CONFIG_SYS_DLL_EXTEND 0x00
178 #define CONFIG_SYS_PCI_HOLD_DEL 0x20
180 #define CONFIG_SYS_ROMNAL 15
181 #define CONFIG_SYS_ROMFAL 31
183 #define CONFIG_SYS_REFINT 430
185 #define CONFIG_SYS_DBUS_SIZE2 1
187 #define CONFIG_SYS_BSTOPRE 121
188 #define CONFIG_SYS_REFREC 8
189 #define CONFIG_SYS_RDLAT 4
190 #define CONFIG_SYS_PRETOACT 3
191 #define CONFIG_SYS_ACTTOPRE 5
192 #define CONFIG_SYS_ACTORW 3
193 #define CONFIG_SYS_SDMODE_CAS_LAT 3
194 #define CONFIG_SYS_SDMODE_WRAP 0
196 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
197 #define CONFIG_SYS_EXTROM 1
198 #define CONFIG_SYS_REGDIMM 0
200 #define CONFIG_SYS_BANK0_START 0x00000000
201 #define CONFIG_SYS_BANK0_END (0x4000000 - 1)
202 #define CONFIG_SYS_BANK0_ENABLE 1
203 #define CONFIG_SYS_BANK1_START 0x04000000
204 #define CONFIG_SYS_BANK1_END (0x8000000 - 1)
205 #define CONFIG_SYS_BANK1_ENABLE 1
206 #define CONFIG_SYS_BANK2_START 0x3ff00000
207 #define CONFIG_SYS_BANK2_END 0x3fffffff
208 #define CONFIG_SYS_BANK2_ENABLE 0
209 #define CONFIG_SYS_BANK3_START 0x3ff00000
210 #define CONFIG_SYS_BANK3_END 0x3fffffff
211 #define CONFIG_SYS_BANK3_ENABLE 0
212 #define CONFIG_SYS_BANK4_START 0x00000000
213 #define CONFIG_SYS_BANK4_END 0x00000000
214 #define CONFIG_SYS_BANK4_ENABLE 0
215 #define CONFIG_SYS_BANK5_START 0x00000000
216 #define CONFIG_SYS_BANK5_END 0x00000000
217 #define CONFIG_SYS_BANK5_ENABLE 0
218 #define CONFIG_SYS_BANK6_START 0x00000000
219 #define CONFIG_SYS_BANK6_END 0x00000000
220 #define CONFIG_SYS_BANK6_ENABLE 0
221 #define CONFIG_SYS_BANK7_START 0x00000000
222 #define CONFIG_SYS_BANK7_END 0x00000000
223 #define CONFIG_SYS_BANK7_ENABLE 0
225 #define CONFIG_SYS_BANK_ENABLE 0x03
227 #define CONFIG_SYS_ODCR 0x75
228 #define CONFIG_SYS_PGMAX 0x32
230 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
231 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
233 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
234 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
236 #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
237 #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
239 #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
240 #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
242 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
243 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
244 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
245 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
246 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
247 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
248 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
249 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
251 #endif /* __CONFIG_H */