1 /* SPDX-License-Identifier: GPL-2.0+ */
3 #ifndef __KONTRON_PITX_IMX8M_H
4 #define __KONTRON_PITX_IMX8M_H
6 #include <linux/sizes.h>
7 #include <linux/stringify.h>
8 #include <asm/arch/imx-regs.h>
10 #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
12 #define CONFIG_SYS_MONITOR_LEN (512 * SZ_1K)
14 /* GUID for capsule updatable firmware image */
15 #define KONTRON_PITX_IMX8M_FIT_IMAGE_GUID \
16 EFI_GUID(0xc898e959, 0x5b1f, 0x4e6d, 0x88, 0xe0, \
17 0x40, 0xd4, 0x5c, 0xca, 0x13, 0x99)
19 #ifdef CONFIG_SPL_BUILD
20 #define CONFIG_SPL_STACK 0x187FF0
21 #define CONFIG_SPL_BSS_START_ADDR 0x00180000
22 #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
23 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
24 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
25 #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
27 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
28 #define CONFIG_MALLOC_F_ADDR 0x182000
29 /* For RAW image gives a error info not panic */
30 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
33 #define CONFIG_POWER_PFUZE100
34 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
38 #if defined(CONFIG_CMD_NET)
39 #define CONFIG_FEC_MXC_PHYADDR 0
41 #define PHY_ANEG_TIMEOUT 20000
45 #define ENV_MEM_LAYOUT_SETTINGS \
46 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
47 "kernel_addr_r=0x42000000\0" \
48 "fdt_addr_r=0x48000000\0" \
49 "fdtoverlay_addr_r=0x49000000\0" \
50 "ramdisk_addr_r=0x48080000\0" \
51 "scriptaddr=0x40000000\0" \
52 "pxefile_addr_r=0x40100000\0"
54 #define BOOT_TARGET_DEVICES(func) \
58 func(DHCP, dhcp, na) \
61 #include <config_distro_bootcmd.h>
63 /* Initial environment variables */
64 #define CONFIG_EXTRA_ENV_SETTINGS \
66 "console=ttymxc2,115200\0" \
68 "fdtfile=freescale/imx8mq-kontron-pitx-imx8m.dtb\0" \
69 "dfu_alt_info=mmc 0=flash-bin raw 0x42 0x1000 mmcpart 1\0"\
70 ENV_MEM_LAYOUT_SETTINGS \
74 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
75 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
76 #define CONFIG_SYS_INIT_SP_OFFSET \
77 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
78 #define CONFIG_SYS_INIT_SP_ADDR \
79 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
81 #define CONFIG_SYS_SDRAM_BASE 0x40000000
82 #define PHYS_SDRAM 0x40000000
83 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
85 #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
87 #define CONFIG_SYS_FSL_USDHC_NUM 2
88 #define CONFIG_SYS_FSL_ESDHC_ADDR 0