1 /* SPDX-License-Identifier: GPL-2.0+ */
3 #ifndef __KONTRON_PITX_IMX8M_H
4 #define __KONTRON_PITX_IMX8M_H
6 #include <linux/sizes.h>
7 #include <linux/stringify.h>
8 #include <asm/arch/imx-regs.h>
10 #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
12 #define CONFIG_SPL_MAX_SIZE (124 * SZ_1K)
13 #define CONFIG_SYS_MONITOR_LEN (512 * SZ_1K)
15 #ifdef CONFIG_SPL_BUILD
16 #define CONFIG_SPL_STACK 0x187FF0
17 #define CONFIG_SPL_BSS_START_ADDR 0x00180000
18 #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
19 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
20 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
21 #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
23 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
24 #define CONFIG_MALLOC_F_ADDR 0x182000
25 /* For RAW image gives a error info not panic */
26 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
29 #define CONFIG_POWER_PFUZE100
30 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
34 #if defined(CONFIG_CMD_NET)
35 #define CONFIG_FEC_MXC_PHYADDR 0
36 #define FEC_QUIRK_ENET_MAC
38 #define IMX_FEC_BASE 0x30BE0000
39 #define PHY_ANEG_TIMEOUT 20000
43 #define ENV_MEM_LAYOUT_SETTINGS \
44 "kernel_addr_r=0x40880000\0" \
45 "fdt_addr_r=0x43000000\0" \
46 "scriptaddr=0x43500000\0" \
47 "initrd_addr=0x43800000\0" \
48 "pxefile_addr_r=0x43500000\0" \
49 "bootm_size=0x10000000\0" \
51 #define BOOT_TARGET_DEVICES(func) \
55 func(DHCP, dhcp, na) \
58 #include <config_distro_bootcmd.h>
60 /* Initial environment variables */
61 #define CONFIG_EXTRA_ENV_SETTINGS \
63 "console=ttymxc2,115200\0" \
65 "fdtfile=freescale/imx8mq-kontron-pitx-imx8m.dtb\0" \
66 "dfu_alt_info=mmc 0=flash-bin raw 0x42 0x1000 mmcpart 1\0"\
67 ENV_MEM_LAYOUT_SETTINGS \
71 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
72 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
73 #define CONFIG_SYS_INIT_SP_OFFSET \
74 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
75 #define CONFIG_SYS_INIT_SP_ADDR \
76 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
78 #define CONFIG_SYS_SDRAM_BASE 0x40000000
79 #define PHYS_SDRAM 0x40000000
80 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
82 #define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
84 #define CONFIG_SYS_FSL_USDHC_NUM 2
85 #define CONFIG_SYS_FSL_ESDHC_ADDR 0