1 /* SPDX-License-Identifier: GPL-2.0+ */
3 #ifndef __KONTRON_PITX_IMX8M_H
4 #define __KONTRON_PITX_IMX8M_H
6 #include <linux/sizes.h>
7 #include <linux/stringify.h>
8 #include <asm/arch/imx-regs.h>
10 #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
12 #define CONFIG_SPL_MAX_SIZE (124 * SZ_1K)
13 #define CONFIG_SYS_MONITOR_LEN (512 * SZ_1K)
15 /* GUID for capsule updatable firmware image */
16 #define KONTRON_PITX_IMX8M_FIT_IMAGE_GUID \
17 EFI_GUID(0xc898e959, 0x5b1f, 0x4e6d, 0x88, 0xe0, \
18 0x40, 0xd4, 0x5c, 0xca, 0x13, 0x99)
20 #ifdef CONFIG_SPL_BUILD
21 #define CONFIG_SPL_STACK 0x187FF0
22 #define CONFIG_SPL_BSS_START_ADDR 0x00180000
23 #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
24 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
25 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
26 #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
28 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
29 #define CONFIG_MALLOC_F_ADDR 0x182000
30 /* For RAW image gives a error info not panic */
31 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
34 #define CONFIG_POWER_PFUZE100
35 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
39 #if defined(CONFIG_CMD_NET)
40 #define CONFIG_FEC_MXC_PHYADDR 0
41 #define FEC_QUIRK_ENET_MAC
43 #define PHY_ANEG_TIMEOUT 20000
47 #define ENV_MEM_LAYOUT_SETTINGS \
48 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
49 "kernel_addr_r=0x42000000\0" \
50 "fdt_addr_r=0x48000000\0" \
51 "fdtoverlay_addr_r=0x49000000\0" \
52 "ramdisk_addr_r=0x48080000\0" \
53 "scriptaddr=0x40000000\0" \
54 "pxefile_addr_r=0x40100000\0"
56 #define BOOT_TARGET_DEVICES(func) \
60 func(DHCP, dhcp, na) \
63 #include <config_distro_bootcmd.h>
65 /* Initial environment variables */
66 #define CONFIG_EXTRA_ENV_SETTINGS \
68 "console=ttymxc2,115200\0" \
70 "fdtfile=freescale/imx8mq-kontron-pitx-imx8m.dtb\0" \
71 "dfu_alt_info=mmc 0=flash-bin raw 0x42 0x1000 mmcpart 1\0"\
72 ENV_MEM_LAYOUT_SETTINGS \
76 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
77 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
78 #define CONFIG_SYS_INIT_SP_OFFSET \
79 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
80 #define CONFIG_SYS_INIT_SP_ADDR \
81 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
83 #define CONFIG_SYS_SDRAM_BASE 0x40000000
84 #define PHYS_SDRAM 0x40000000
85 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
87 #define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
89 #define CONFIG_SYS_FSL_USDHC_NUM 2
90 #define CONFIG_SYS_FSL_ESDHC_ADDR 0