include/configs/kmvect1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 #define CONFIG_HOSTNAME         "kmvect1"
  24 #define CONFIG_KM_BOARD_NAME   "kmvect1"
  25 /* at end of uboot partition, before env */
  26 #define CONFIG_SYS_QE_FW_ADDR   0xF00B0000
  27
  28 /*
  29  * High Level Configuration Options
  30  */
  31 #define CONFIG_E300             1       /* E300 family */
  32 #define CONFIG_QE               1       /* Has QE */
  33
  34 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
  35
  36 /* include common defines/options for all Keymile boards */
  37 #include "km/keymile-common.h"
  38 #include "km/km-powerpc.h"
  39
  40 /*
  41  * System Clock Setup
  42  */
  43 #define CONFIG_83XX_CLKIN               66000000
  44 #define CONFIG_SYS_CLK_FREQ             66000000
  45 #define CONFIG_83XX_PCICLK              66000000
  46
  47 /*
  48  * DDR Setup
  49  */
  50 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  51 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  52 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  53
  54 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  55 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  56                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  57
  58 #define CFG_83XX_DDR_USES_CS0
  59
  60 /*
  61  * Manually set up DDR parameters
  62  */
  63 #define CONFIG_DDR_II
  64 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  65
  66 /*
  67  * The reserved memory
  68  */
  69 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  70 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  71
  72 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  73 #define CONFIG_SYS_RAMBOOT
  74 #endif
  75
  76 /* Reserve 768 kB for Mon */
  77 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  78
  79 /*
  80  * Initial RAM Base Address Setup
  81  */
  82 #define CONFIG_SYS_INIT_RAM_LOCK
  83 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  84 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  85 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  86                                                 GENERATED_GBL_DATA_SIZE)
  87
  88 /*
  89  * Init Local Bus Memory Controller:
  90  *
  91  * Bank Bus     Machine PortSz  Size  Device
  92  * ---- ---     ------- ------  -----  ------
  93  *  0   Local   GPCM    16 bit  256MB FLASH
  94  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
  95  *
  96  */
  97 /*
  98  * FLASH on the Local Bus
  99  */
 100 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 101
 102
 103 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 104 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 105 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 106
 107 /*
 108  * PRIO1/PIGGY on the local bus CS1
 109  */
 110
 111
 112 /*
 113  * Serial Port
 114  */
 115 #define CONFIG_SYS_NS16550_SERIAL
 116 #define CONFIG_SYS_NS16550_REG_SIZE     1
 117 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 118
 119 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 120 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 121
 122 /*
 123  * QE UEC ethernet configuration
 124  */
 125 #define CONFIG_UEC_ETH
 126 #define CONFIG_ETHPRIME         "UEC0"
 127
 128 #ifdef CONFIG_UEC_ETH1
 129 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 130 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 131 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 132 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 133 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 134 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 135 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 136 #endif
 137
 138 /*
 139  * Environment
 140  */
 141
 142 #ifndef CONFIG_SYS_RAMBOOT
 143 #ifndef CONFIG_ENV_ADDR
 144 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 145                                         CONFIG_SYS_MONITOR_LEN)
 146 #endif
 147 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 148 #ifndef CONFIG_ENV_OFFSET
 149 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 150 #endif
 151
 152 /* Address and size of Redundant Environment Sector     */
 153 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 154                                                 CONFIG_ENV_SECT_SIZE)
 155 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 156
 157 #else /* CFG_SYS_RAMBOOT */
 158 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 159 #define CONFIG_ENV_SIZE         0x2000
 160 #endif /* CFG_SYS_RAMBOOT */
 161
 162 /* I2C */
 163 #define CONFIG_SYS_I2C
 164 #define CONFIG_SYS_NUM_I2C_BUSES        4
 165 #define CONFIG_SYS_I2C_MAX_HOPS         1
 166 #define CONFIG_SYS_I2C_FSL
 167 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 168 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 169 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 170 #define CONFIG_SYS_I2C_OFFSET           0x3000
 171 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 172 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 173 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 174 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 175                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 176                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 177                 {1, {I2C_NULL_HOP} } }
 178
 179 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 180
 181 #if defined(CONFIG_CMD_NAND)
 182 #define CONFIG_NAND_KMETER1
 183 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 184 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 185 #endif
 186
 187 /*
 188  * For booting Linux, the board info and command line data
 189  * have to be in the first 8 MB of memory, since this is
 190  * the maximum mapped by the Linux kernel during initialization.
 191  */
 192 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 193
 194 /*
 195  * Internal Definitions
 196  */
 197 #define BOOTFLASH_START 0xF0000000
 198
 199 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 200
 201 /*
 202  * Environment Configuration
 203  */
 204 #define CONFIG_ENV_OVERWRITE
 205 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 206 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 207 #endif
 208
 209 #ifndef CONFIG_KM_DEF_ARCH
 210 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 211 #endif
 212
 213 #define CONFIG_EXTRA_ENV_SETTINGS \
 214         CONFIG_KM_DEF_ENV                                               \
 215         CONFIG_KM_DEF_ARCH                                              \
 216         "newenv="                                                       \
 217                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 218                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 219         "unlock=yes\0"                                                  \
 220         ""
 221
 222 #if defined(CONFIG_UEC_ETH)
 223 #define CONFIG_HAS_ETH0
 224 #endif
 225
 226 /* QE microcode/firmware address */
 227 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 228 /* between the u-boot partition and env */
 229 #ifndef CONFIG_SYS_QE_FW_ADDR
 230 #define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
 231 #endif
 232
 233 /*
 234  * System IO Config
 235  */
 236 /* 0x14000180 SICR_1 */
 237 #define CONFIG_SYS_SICRL (0                     \
 238                 | SICR_1_UART1_UART1RTS         \
 239                 | SICR_1_I2C_CKSTOP             \
 240                 | SICR_1_IRQ_A_IRQ              \
 241                 | SICR_1_IRQ_B_IRQ              \
 242                 | SICR_1_GPIO_A_GPIO            \
 243                 | SICR_1_GPIO_B_GPIO            \
 244                 | SICR_1_GPIO_C_GPIO            \
 245                 | SICR_1_GPIO_D_GPIO            \
 246                 | SICR_1_GPIO_E_GPIO            \
 247                 | SICR_1_GPIO_F_GPIO            \
 248                 | SICR_1_USB_A_UART2S           \
 249                 | SICR_1_USB_B_UART2RTS         \
 250                 | SICR_1_FEC1_FEC1              \
 251                 | SICR_1_FEC2_FEC2              \
 252                 )
 253
 254 /* 0x00080400 SICR_2 */
 255 #define CONFIG_SYS_SICRH (0                     \
 256                 | SICR_2_FEC3_FEC3              \
 257                 | SICR_2_HDLC1_A_HDLC1          \
 258                 | SICR_2_ELBC_A_LA              \
 259                 | SICR_2_ELBC_B_LCLK            \
 260                 | SICR_2_HDLC2_A_HDLC2          \
 261                 | SICR_2_USB_D_GPIO             \
 262                 | SICR_2_PCI_PCI                \
 263                 | SICR_2_HDLC1_B_HDLC1          \
 264                 | SICR_2_HDLC1_C_HDLC1          \
 265                 | SICR_2_HDLC2_B_GPIO           \
 266                 | SICR_2_HDLC2_C_HDLC2          \
 267                 | SICR_2_QUIESCE_B              \
 268                 )
 269
 270 /* GPR_1 */
 271 #define CONFIG_SYS_GPR1  0x50008060
 272
 273 #define CONFIG_SYS_GP1DIR 0x00000000
 274 #define CONFIG_SYS_GP1ODR 0x00000000
 275 #define CONFIG_SYS_GP2DIR 0xFF000000
 276 #define CONFIG_SYS_GP2ODR 0x00000000
 277
 278 #define CONFIG_SYS_DDRCDR (\
 279         DDRCDR_EN | \
 280         DDRCDR_PZ_MAXZ | \
 281         DDRCDR_NZ_MAXZ | \
 282         DDRCDR_M_ODR)
 283
 284 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 285 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 286                                          SDRAM_CFG_32_BE | \
 287                                          SDRAM_CFG_SREN | \
 288                                          SDRAM_CFG_HSE)
 289
 290 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 291 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 292 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 293                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 294
 295 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 296                                          CSCONFIG_ODT_RD_NEVER | \
 297                                          CSCONFIG_ODT_WR_ONLY_CURRENT | \
 298                                          CSCONFIG_ROW_BIT_13 | \
 299                                          CSCONFIG_COL_BIT_10)
 300
 301 #define CONFIG_SYS_DDR_MODE     0x47860242
 302 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 303
 304 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 305                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 306                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 307                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 308                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 309                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 310                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 311                                  (0 << TIMING_CFG0_RWT_SHIFT))
 312
 313 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 314                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 315                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 316                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 317                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 318                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 319                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 320                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 321
 322 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 323                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 324                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 325                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 326                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 327                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 328                                  (5 << TIMING_CFG2_CPO_SHIFT))
 329
 330 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 331
 332 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 333 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 334
 335 /* EEprom support */
 336 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 337
 338 /*
 339  * Local Bus Configuration & Clock Setup
 340  */
 341 #define CONFIG_SYS_LBC_LBCR     0x00000000
 342
 343 #define CONFIG_SYS_APP1_BASE            0xA0000000
 344 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
 345 #define CONFIG_SYS_APP2_BASE            0xB0000000
 346 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
 347
 348 /* EEprom support */
 349 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 350
 351 /*
 352  * Init Local Bus Memory Controller:
 353  *
 354  * Bank Bus     Machine PortSz  Size  Device
 355  * ---- ---     ------- ------  -----  ------
 356  *  2   Local   UPMA    16 bit  256MB APP1
 357  *  3   Local   GPCM    16 bit  256MB APP2
 358  *
 359  */
 360
 361
 362
 363 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
 364                          0x0000c000 | \
 365                          MxMR_WLFx_2X)
 366 /*
 367  * QE UEC ethernet configuration
 368  */
 369 #define CONFIG_MV88E6352_SWITCH
 370 #define CONFIG_KM_MVEXTSW_ADDR          0x10
 371
 372 /* ethernet port connected to simple switch 88e6122 (UEC0) */
 373 #define CONFIG_UEC_ETH1
 374 #define CONFIG_SYS_UEC1_UCC_NUM         0       /* UCC1 */
 375 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 376 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 377
 378 #define CONFIG_FIXED_PHY                0xFFFFFFFF
 379 #define CONFIG_SYS_FIXED_PHY_ADDR       0x1E    /* unused address */
 380 #define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
 381                 {devnum, speed, duplex}
 382 #define CONFIG_SYS_FIXED_PHY_PORTS \
 383                 CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
 384
 385 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 386 #define CONFIG_SYS_UEC1_PHY_ADDR        CONFIG_SYS_FIXED_PHY_ADDR
 387 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 388 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 389
 390 /* ethernet port connected to piggy (UEC2) */
 391 #define CONFIG_HAS_ETH1
 392 #define CONFIG_UEC_ETH2
 393 #define CONFIG_SYS_UEC2_UCC_NUM         2       /* UCC3 */
 394 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 395 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK12
 396 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 397 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 398 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 399 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 400
 401 #endif /* __CONFIG_H */