1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * Copyright (C) 2007 Logic Product Development, Inc.
7 * Peter Barada <peterb@logicpd.com>
9 * Copyright (C) 2007 MontaVista Software, Inc.
10 * Anton Vorontsov <avorontsov@ru.mvista.com>
13 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
20 * High Level Configuration Options
23 #define CONFIG_HOSTNAME "kmtegr1"
24 #define CONFIG_KM_BOARD_NAME "kmtegr1"
25 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
26 #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
28 #define CONFIG_ENV_ADDR 0xF0100000
29 #define CONFIG_ENV_OFFSET 0x100000
31 #define CONFIG_NAND_ECC_BCH
32 #define CONFIG_NAND_KMETER1
33 #define CONFIG_SYS_MAX_NAND_DEVICE 1
34 #define NAND_MAX_CHIPS 1
37 * High Level Configuration Options
39 #define CONFIG_E300 1 /* E300 family */
40 #define CONFIG_QE 1 /* Has QE */
42 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
44 /* include common defines/options for all Keymile boards */
45 #include "km/keymile-common.h"
46 #include "km/km-powerpc.h"
51 #define CONFIG_83XX_CLKIN 66000000
52 #define CONFIG_SYS_CLK_FREQ 66000000
53 #define CONFIG_83XX_PCICLK 66000000
58 #define CONFIG_SYS_IMMR 0xE0000000
61 * Bus Arbitration Configuration Register (ACR)
63 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
64 #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
65 #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
66 #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
71 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
72 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
73 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
75 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
76 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
77 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
79 #define CFG_83XX_DDR_USES_CS0
82 * Manually set up DDR parameters
85 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */
90 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
91 #define CONFIG_SYS_FLASH_BASE 0xF0000000
93 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
94 #define CONFIG_SYS_RAMBOOT
97 /* Reserve 768 kB for Mon */
98 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
101 * Initial RAM Base Address Setup
103 #define CONFIG_SYS_INIT_RAM_LOCK
104 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
105 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
106 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
107 GENERATED_GBL_DATA_SIZE)
110 * Init Local Bus Memory Controller:
112 * Bank Bus Machine PortSz Size Device
113 * ---- --- ------- ------ ----- ------
114 * 0 Local GPCM 16 bit 256MB FLASH
115 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
119 * FLASH on the Local Bus
121 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
123 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
124 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
126 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
127 BR_PS_16 | /* 16 bit port size */ \
128 BR_MS_GPCM | /* MSEL = GPCM */ \
131 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
132 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
134 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
136 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
137 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
138 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
141 * PRIO1/PIGGY on the local bus CS1
143 /* Window base at flash base */
144 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE
145 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
147 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \
148 BR_PS_8 | /* 8 bit port size */ \
149 BR_MS_GPCM | /* MSEL = GPCM */ \
151 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
152 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
154 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
159 #define CONFIG_SYS_NS16550_SERIAL
160 #define CONFIG_SYS_NS16550_REG_SIZE 1
161 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
163 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
164 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
167 * QE UEC ethernet configuration
169 #define CONFIG_UEC_ETH
170 #define CONFIG_ETHPRIME "UEC0"
172 #ifdef CONFIG_UEC_ETH1
173 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
174 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
175 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
176 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
177 #define CONFIG_SYS_UEC1_PHY_ADDR 0
178 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
179 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
186 #ifndef CONFIG_SYS_RAMBOOT
187 #ifndef CONFIG_ENV_ADDR
188 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
189 CONFIG_SYS_MONITOR_LEN)
191 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
192 #ifndef CONFIG_ENV_OFFSET
193 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
196 /* Address and size of Redundant Environment Sector */
197 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
198 CONFIG_ENV_SECT_SIZE)
199 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
201 #else /* CFG_SYS_RAMBOOT */
202 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
203 #define CONFIG_ENV_SIZE 0x2000
204 #endif /* CFG_SYS_RAMBOOT */
207 #define CONFIG_SYS_I2C
208 #define CONFIG_SYS_NUM_I2C_BUSES 4
209 #define CONFIG_SYS_I2C_MAX_HOPS 1
210 #define CONFIG_SYS_I2C_FSL
211 #define CONFIG_SYS_FSL_I2C_SPEED 200000
212 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
213 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
214 #define CONFIG_SYS_I2C_OFFSET 0x3000
215 #define CONFIG_SYS_FSL_I2C2_SPEED 200000
216 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
217 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
218 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
219 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
220 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
221 {1, {I2C_NULL_HOP} } }
223 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
225 #if defined(CONFIG_CMD_NAND)
226 #define CONFIG_NAND_KMETER1
227 #define CONFIG_SYS_MAX_NAND_DEVICE 1
228 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
232 * For booting Linux, the board info and command line data
233 * have to be in the first 8 MB of memory, since this is
234 * the maximum mapped by the Linux kernel during initialization.
236 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
241 #define CONFIG_SYS_HID0_INIT 0x000000000
242 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
243 HID0_ENABLE_INSTRUCTION_CACHE)
244 #define CONFIG_SYS_HID2 HID2_HBE
250 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
252 /* DDR: cache cacheable */
253 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
254 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
255 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
257 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
258 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
260 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
261 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
262 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
263 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
265 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
266 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
268 /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
269 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
271 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
273 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
274 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
275 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
277 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
278 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
280 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
282 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
283 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
284 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
286 /* Stack in dcache: cacheable, no memory coherence */
287 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
288 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
290 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
291 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
294 * Internal Definitions
296 #define BOOTFLASH_START 0xF0000000
298 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
301 * Environment Configuration
303 #define CONFIG_ENV_OVERWRITE
304 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
305 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
308 #ifndef CONFIG_KM_DEF_ARCH
309 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
312 #define CONFIG_EXTRA_ENV_SETTINGS \
316 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \
317 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \
321 #if defined(CONFIG_UEC_ETH)
322 #define CONFIG_HAS_ETH0
325 /* QE microcode/firmware address */
326 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
327 /* between the u-boot partition and env */
328 #ifndef CONFIG_SYS_QE_FW_ADDR
329 #define CONFIG_SYS_QE_FW_ADDR 0xF00C0000
335 /* 0x14000180 SICR_1 */
336 #define CONFIG_SYS_SICRL (0 \
337 | SICR_1_UART1_UART1RTS \
338 | SICR_1_I2C_CKSTOP \
341 | SICR_1_GPIO_A_GPIO \
342 | SICR_1_GPIO_B_GPIO \
343 | SICR_1_GPIO_C_GPIO \
344 | SICR_1_GPIO_D_GPIO \
345 | SICR_1_GPIO_E_GPIO \
346 | SICR_1_GPIO_F_GPIO \
347 | SICR_1_USB_A_UART2S \
348 | SICR_1_USB_B_UART2RTS \
353 /* 0x00080400 SICR_2 */
354 #define CONFIG_SYS_SICRH (0 \
356 | SICR_2_HDLC1_A_HDLC1 \
358 | SICR_2_ELBC_B_LCLK \
359 | SICR_2_HDLC2_A_HDLC2 \
360 | SICR_2_USB_D_GPIO \
362 | SICR_2_HDLC1_B_HDLC1 \
363 | SICR_2_HDLC1_C_HDLC1 \
364 | SICR_2_HDLC2_B_GPIO \
365 | SICR_2_HDLC2_C_HDLC2 \
370 #define CONFIG_SYS_GPR1 0x50008060
372 #define CONFIG_SYS_GP1DIR 0x00000000
373 #define CONFIG_SYS_GP1ODR 0x00000000
374 #define CONFIG_SYS_GP2DIR 0xFF000000
375 #define CONFIG_SYS_GP2ODR 0x00000000
378 * Hardware Reset Configuration Word
380 #define CONFIG_SYS_HRCW_LOW (\
381 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
382 HRCWL_DDR_TO_SCB_CLK_2X1 | \
383 HRCWL_CSB_TO_CLKIN_2X1 | \
384 HRCWL_CORE_TO_CSB_2X1 | \
385 HRCWL_CE_PLL_VCO_DIV_2 | \
388 #define CONFIG_SYS_HRCW_HIGH (\
390 HRCWH_PCI_ARBITER_DISABLE | \
391 HRCWH_CORE_ENABLE | \
392 HRCWH_FROM_0X00000100 | \
393 HRCWH_BOOTSEQ_DISABLE | \
394 HRCWH_SW_WATCHDOG_DISABLE | \
395 HRCWH_ROM_LOC_LOCAL_16BIT | \
399 #define CONFIG_SYS_DDRCDR (\
405 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
406 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
411 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
412 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
413 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
414 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
416 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
417 CSCONFIG_ODT_RD_NEVER | \
418 CSCONFIG_ODT_WR_ONLY_CURRENT | \
419 CSCONFIG_ROW_BIT_13 | \
422 #define CONFIG_SYS_DDR_MODE 0x47860242
423 #define CONFIG_SYS_DDR_MODE2 0x8080c000
425 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
426 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
427 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
428 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
429 (0 << TIMING_CFG0_WWT_SHIFT) | \
430 (0 << TIMING_CFG0_RRT_SHIFT) | \
431 (0 << TIMING_CFG0_WRT_SHIFT) | \
432 (0 << TIMING_CFG0_RWT_SHIFT))
434 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
435 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
436 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
437 (3 << TIMING_CFG1_WRREC_SHIFT) | \
438 (7 << TIMING_CFG1_REFREC_SHIFT) | \
439 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
440 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
441 (3 << TIMING_CFG1_PRETOACT_SHIFT))
443 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
444 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
445 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
446 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
447 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
448 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
449 (5 << TIMING_CFG2_CPO_SHIFT))
451 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
453 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
454 #define CONFIG_SYS_KMBEC_FPGA_SIZE 128
457 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
460 * Local Bus Configuration & Clock Setup
462 #define CONFIG_SYS_LCRR_DBYP 0x80000000
463 #define CONFIG_SYS_LCRR_EADC 0x00010000
464 #define CONFIG_SYS_LCRR_CLKDIV 0x00000002
466 #define CONFIG_SYS_LBC_LBCR 0x00000000
471 #define CONFIG_SYS_IBAT7L (0)
472 #define CONFIG_SYS_IBAT7U (0)
473 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
474 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
476 /* must be after the include because KMBEC_FPGA is otherwise undefined */
477 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
479 #define CONFIG_SYS_APP1_BASE 0xA0000000
480 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
481 #define CONFIG_SYS_APP2_BASE 0xB0000000
482 #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
485 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
488 * Init Local Bus Memory Controller:
490 * Bank Bus Machine PortSz Size Device
491 * ---- --- ------- ------ ----- ------
492 * 2 Local UPMA 16 bit 256MB APP1
493 * 3 Local GPCM 16 bit 256MB APP2
497 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
502 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
504 OR_GPCM_TRLX_CLEAR | \
507 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
508 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
513 #define CONFIG_SYS_IBAT5L (0)
514 #define CONFIG_SYS_IBAT5U (0)
515 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
516 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
517 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
519 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
521 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
522 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
523 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
525 /* ethernet port connected to piggy (UEC2) */
526 #define CONFIG_HAS_ETH1
527 #define CONFIG_UEC_ETH2
528 #define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
529 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
530 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
531 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
532 #define CONFIG_SYS_UEC2_PHY_ADDR 0
533 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
534 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
536 #endif /* __CONFIG_H */