include/configs/kmsupx5.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2008
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  *
  15  * (C) Copyright 2010-2013
  16  * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
  17  * Holger Brunck,  Keymile GmbH, holger.bruncl@keymile.com
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  */
  26 #define CONFIG_KM_BOARD_NAME    "kmsupx5"
  27 #define CONFIG_HOSTNAME         "kmsupx5"
  28
  29 /*
  30  * High Level Configuration Options
  31  */
  32 #define CONFIG_QE       /* Has QE */
  33 #define CONFIG_KM8321   /* Keymile PBEC8321 board specific */
  34
  35 #define CONFIG_KM_DEF_ARCH      "arch=ppc_8xx\0"
  36
  37 /* include common defines/options for all Keymile boards */
  38 #include "km/keymile-common.h"
  39 #include "km/km-powerpc.h"
  40
  41 /*
  42  * System Clock Setup
  43  */
  44 #define CONFIG_83XX_CLKIN               66000000
  45 #define CONFIG_SYS_CLK_FREQ             66000000
  46 #define CONFIG_83XX_PCICLK              66000000
  47
  48 /*
  49  * IMMR new address
  50  */
  51 #define CONFIG_SYS_IMMR         0xE0000000
  52
  53 /*
  54  * Bus Arbitration Configuration Register (ACR)
  55  */
  56 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  57 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  58 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  59 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  60
  61 /*
  62  * DDR Setup
  63  */
  64 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  65 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  66 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  67
  68 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  69 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  70                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  71
  72 #define CFG_83XX_DDR_USES_CS0
  73
  74 /*
  75  * Manually set up DDR parameters
  76  */
  77 #define CONFIG_DDR_II
  78 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  79
  80 /*
  81  * The reserved memory
  82  */
  83 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  84 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  85
  86 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  87 #define CONFIG_SYS_RAMBOOT
  88 #endif
  89
  90 /* Reserve 768 kB for Mon */
  91 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  92
  93 /*
  94  * Initial RAM Base Address Setup
  95  */
  96 #define CONFIG_SYS_INIT_RAM_LOCK
  97 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  98 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  99 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 100                                                 GENERATED_GBL_DATA_SIZE)
 101
 102 /*
 103  * Init Local Bus Memory Controller:
 104  *
 105  * Bank Bus     Machine PortSz  Size  Device
 106  * ---- ---     ------- ------  -----  ------
 107  *  0   Local   GPCM    16 bit  256MB FLASH
 108  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 109  *
 110  */
 111 /*
 112  * FLASH on the Local Bus
 113  */
 114 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 115
 116 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 117                                 BR_PS_16 | /* 16 bit port size */ \
 118                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 119                                 BR_V)
 120
 121 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_256MB | \
 122                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 123                                 OR_GPCM_SCY_5 | \
 124                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 125
 126 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 127 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 128 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 129
 130 /*
 131  * PRIO1/PIGGY on the local bus CS1
 132  */
 133 /* Window base at flash base */
 134 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_KMBEC_FPGA_BASE | \
 135                                 BR_PS_8 | /* 8 bit port size */ \
 136                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 137                                 BR_V)
 138 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_128MB | \
 139                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 140                                 OR_GPCM_SCY_2 | \
 141                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 142
 143 /*
 144  * Serial Port
 145  */
 146 #define CONFIG_SYS_NS16550_SERIAL
 147 #define CONFIG_SYS_NS16550_REG_SIZE     1
 148 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 149
 150 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 151 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 152
 153 /*
 154  * QE UEC ethernet configuration
 155  */
 156 #define CONFIG_UEC_ETH
 157 #define CONFIG_ETHPRIME         "UEC0"
 158
 159 #define CONFIG_UEC_ETH1         /* GETH1 */
 160 #define UEC_VERBOSE_DEBUG       1
 161
 162 #ifdef CONFIG_UEC_ETH1
 163 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 164 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 165 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 166 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 167 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 168 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 169 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 170 #endif
 171
 172 /*
 173  * Environment
 174  */
 175
 176 #ifndef CONFIG_SYS_RAMBOOT
 177 #ifndef CONFIG_ENV_ADDR
 178 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 179                                         CONFIG_SYS_MONITOR_LEN)
 180 #endif
 181 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 182 #ifndef CONFIG_ENV_OFFSET
 183 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 184 #endif
 185
 186 /* Address and size of Redundant Environment Sector     */
 187 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 188                                                 CONFIG_ENV_SECT_SIZE)
 189 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 190
 191 #else /* CFG_SYS_RAMBOOT */
 192 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 193 #define CONFIG_ENV_SIZE         0x2000
 194 #endif /* CFG_SYS_RAMBOOT */
 195
 196 /* I2C */
 197 #define CONFIG_SYS_I2C
 198 #define CONFIG_SYS_NUM_I2C_BUSES        4
 199 #define CONFIG_SYS_I2C_MAX_HOPS         1
 200 #define CONFIG_SYS_I2C_FSL
 201 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 202 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 203 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 204 #define CONFIG_SYS_I2C_OFFSET           0x3000
 205 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 206 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 207 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 208 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 209                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 210                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 211                 {1, {I2C_NULL_HOP} } }
 212
 213 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 214
 215 #if defined(CONFIG_CMD_NAND)
 216 #define CONFIG_NAND_KMETER1
 217 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 218 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 219 #endif
 220
 221 /*
 222  * For booting Linux, the board info and command line data
 223  * have to be in the first 8 MB of memory, since this is
 224  * the maximum mapped by the Linux kernel during initialization.
 225  */
 226 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 227
 228 /*
 229  * Core HID Setup
 230  */
 231 #define CONFIG_SYS_HID0_INIT            0x000000000
 232 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 233                                          HID0_ENABLE_INSTRUCTION_CACHE)
 234 #define CONFIG_SYS_HID2                 HID2_HBE
 235
 236 /*
 237  * Internal Definitions
 238  */
 239 #define BOOTFLASH_START 0xF0000000
 240
 241 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 242
 243 /*
 244  * Environment Configuration
 245  */
 246 #define CONFIG_ENV_OVERWRITE
 247 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 248 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 249 #endif
 250
 251 #ifndef CONFIG_KM_DEF_ARCH
 252 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 253 #endif
 254
 255 #define CONFIG_EXTRA_ENV_SETTINGS \
 256         CONFIG_KM_DEF_ENV                                               \
 257         CONFIG_KM_DEF_ARCH                                              \
 258         "newenv="                                                       \
 259                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 260                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 261         "unlock=yes\0"                                                  \
 262         ""
 263
 264 #if defined(CONFIG_UEC_ETH)
 265 #define CONFIG_HAS_ETH0
 266 #endif
 267
 268 /*
 269  * System IO Config
 270  */
 271 #define CONFIG_SYS_SICRL        SICRL_IRQ_CKS
 272
 273 #define CONFIG_SYS_DDRCDR (\
 274         DDRCDR_EN | \
 275         DDRCDR_PZ_MAXZ | \
 276         DDRCDR_NZ_MAXZ | \
 277         DDRCDR_M_ODR)
 278
 279 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 280 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 281                                          SDRAM_CFG_32_BE | \
 282                                          SDRAM_CFG_SREN | \
 283                                          SDRAM_CFG_HSE)
 284
 285 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 286 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 287 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 288                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 289
 290 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 291                                          CSCONFIG_ODT_WR_CFG | \
 292                                          CSCONFIG_ROW_BIT_13 | \
 293                                          CSCONFIG_COL_BIT_10)
 294
 295 #define CONFIG_SYS_DDR_MODE     0x47860242
 296 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 297
 298 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 299                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 300                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 301                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 302                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 303                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 304                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 305                                  (0 << TIMING_CFG0_RWT_SHIFT))
 306
 307 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 308                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 309                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 310                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 311                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 312                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 313                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 314                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 315
 316 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 317                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 318                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 319                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 320                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 321                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 322                                  (5 << TIMING_CFG2_CPO_SHIFT))
 323
 324 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 325
 326 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 327 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 328
 329 /* EEprom support */
 330 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 331
 332 /*
 333  * Local Bus Configuration & Clock Setup
 334  */
 335 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 336 #define CONFIG_SYS_LCRR_EADC    0x00010000
 337 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 338
 339 #define CONFIG_SYS_LBC_LBCR     0x00000000
 340
 341 #define CONFIG_SYS_APP1_BASE    0xA0000000    /* PAXG */
 342 #define CONFIG_SYS_APP1_SIZE    256 /* Megabytes */
 343
 344 /*
 345  * Init Local Bus Memory Controller:
 346  *                                    Device on board
 347  * Bank Bus     Machine PortSz Size   TUDA1  TUXA1  TUGE1   KMSUPX4 KMOPTI2
 348  * -----------------------------------------------------------------------------
 349  *  2   Local   GPCM    8 bit  256MB  PAXG   LPXF   PAXI    LPXF    PAXE
 350  *  3   Local   GPCM    8 bit  256MB  PINC3  PINC2  unused  unused  OPI2(16 bit)
 351  *
 352  *                                    Device on board (continued)
 353  * Bank Bus     Machine PortSz Size   KMTEPR2
 354  * -----------------------------------------------------------------------------
 355  *  2   Local   GPCM    8 bit  256MB  NVRAM
 356  *  3   Local   GPCM    8 bit  256MB  TEP2 (16 bit)
 357  */
 358
 359 /*
 360  * Configuration for C2 on the local bus
 361  */
 362 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_APP1_BASE | \
 363                                  BR_PS_8 | \
 364                                  BR_MS_GPCM | \
 365                                  BR_V)
 366
 367 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_256MB | \
 368                                  OR_GPCM_CSNT | \
 369                                  OR_GPCM_ACS_DIV4 | \
 370                                  OR_GPCM_SCY_2 | \
 371                                  OR_GPCM_TRLX_SET | \
 372                                  OR_GPCM_EHTR_CLEAR | \
 373                                  OR_GPCM_EAD)
 374
 375 #endif /* __CONFIG_H */