include/configs/kmp204x.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2013 Keymile AG
   4  * Valentin Longchamp <valentin.longchamp@keymile.com>
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #if defined(CONFIG_KMCOGE4)
  11 #define CONFIG_HOSTNAME         "kmcoge4"
  12
  13 #else
  14 #error ("Board not supported")
  15 #endif
  16
  17 #define CONFIG_KMP204X
  18
  19 /* an additionnal option is required for UBI as subpage access is
  20  * supported in u-boot
  21  */
  22 #define CONFIG_KM_UBI_PART_BOOT_OPTS            ",2048"
  23
  24 #define CONFIG_NAND_ECC_BCH
  25
  26 /* common KM defines */
  27 #include "km/keymile-common.h"
  28
  29 #define CONFIG_SYS_RAMBOOT
  30 #define CONFIG_RAMBOOT_PBL
  31 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  32 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  33 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
  34 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
  35
  36 /* High Level Configuration Options */
  37 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  38 #define CONFIG_FSL_CORENET              /* Freescale CoreNet platform */
  39
  40 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  41 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  42 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  43 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  44 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  45 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  46
  47 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  48
  49 /* Environment in SPI Flash */
  50 #define CONFIG_ENV_TOTAL_SIZE           0x020000
  51
  52 #ifndef __ASSEMBLY__
  53 unsigned long get_board_sys_clk(unsigned long dummy);
  54 #endif
  55 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  56
  57 /*
  58  * These can be toggled for performance analysis, otherwise use default.
  59  */
  60 #define CONFIG_SYS_CACHE_STASHING
  61 #define CONFIG_BACKSIDE_L2_CACHE
  62 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  63 #define CONFIG_BTB                      /* toggle branch predition */
  64
  65 #define CONFIG_ENABLE_36BIT_PHYS
  66
  67 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
  68
  69 /*
  70  *  Config the L3 Cache as L3 SRAM
  71  */
  72 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  73 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  74                 CONFIG_RAMBOOT_TEXT_BASE)
  75 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  76 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  77
  78 #define CONFIG_SYS_DCSRBAR              0xf0000000
  79 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  80
  81 /*
  82  * DDR Setup
  83  */
  84 #define CONFIG_VERY_BIG_RAM
  85 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  86 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  87
  88 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  89 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  90
  91 #define CONFIG_DDR_SPD
  92
  93 #define CONFIG_SYS_SPD_BUS_NUM  0
  94 #define SPD_EEPROM_ADDRESS      0x54
  95 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
  96
  97 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
  98 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
  99
 100 /******************************************************************************
 101  * (PRAM usage)
 102  * ... -------------------------------------------------------
 103  * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
 104  * ... |<------------------- pram -------------------------->|
 105  * ... -------------------------------------------------------
 106  * @END_OF_RAM:
 107  * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
 108  * @CONFIG_KM_PHRAM: address for /var
 109  * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
 110  * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
 111  */
 112
 113 /* size of rootfs in RAM */
 114 #define CONFIG_KM_ROOTFSSIZE    0x0
 115 /* pseudo-non volatile RAM [hex] */
 116 #define CONFIG_KM_PNVRAM        0x80000
 117 /* physical RAM MTD size [hex] */
 118 #define CONFIG_KM_PHRAM         0x100000
 119 /* reserved pram area at the end of memory [hex]
 120  * u-boot reserves some memory for the MP boot page
 121  */
 122 #define CONFIG_KM_RESERVED_PRAM 0x1000
 123 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
 124  * is not valid yet, which is the case for when u-boot copies itself to RAM
 125  */
 126 #define CONFIG_PRAM             ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
 127
 128 /*
 129  * Local Bus Definitions
 130  */
 131
 132 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
 133 #define CONFIG_SYS_LBC_LCRR             (LCRR_CLKDIV_8 | LCRR_EADC_2)
 134
 135 /* Nand Flash */
 136 #define CONFIG_NAND_FSL_ELBC
 137 #define CONFIG_SYS_NAND_BASE            0xffa00000
 138 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 139
 140 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 141 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 142 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 143
 144 /* NAND flash config */
 145 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 146                                | BR_PS_8               /* Port Size = 8 bit */ \
 147                                | BR_MS_FCM             /* MSEL = FCM */ \
 148                                | BR_V)                 /* valid */
 149
 150 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB       /* length 256K */ \
 151                                | OR_FCM_BCTLD   /* LBCTL not ass */     \
 152                                | OR_FCM_SCY_1   /* 1 clk wait cycle */  \
 153                                | OR_FCM_RST     /* 1 clk read setup */  \
 154                                | OR_FCM_PGS     /* Large page size */   \
 155                                | OR_FCM_CST)    /* 0.25 command setup */
 156
 157 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 158 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 159
 160 /* QRIO FPGA */
 161 #define CONFIG_SYS_QRIO_BASE            0xfb000000
 162 #define CONFIG_SYS_QRIO_BASE_PHYS       0xffb000000ull
 163
 164 #define CONFIG_SYS_QRIO_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
 165                                 | BR_PS_8       /* Port Size 8 bits */ \
 166                                 | BR_DECC_OFF   /* no error corr */ \
 167                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 168                                 | BR_V)         /* valid */
 169
 170 #define CONFIG_SYS_QRIO_OR_PRELIM  (OR_AM_64KB  /* length 64K */ \
 171                                 | OR_GPCM_BCTLD /* no LCTL assert */ \
 172                                 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
 173                                 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
 174                                 | OR_GPCM_TRLX /* relaxed tmgs */ \
 175                                 | OR_GPCM_EAD) /* extra bus clk cycles */
 176
 177 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
 178 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
 179
 180 #define CONFIG_MISC_INIT_F
 181
 182 #define CONFIG_HWCONFIG
 183
 184 /* define to use L1 as initial stack */
 185 #define CONFIG_L1_INIT_RAM
 186 #define CONFIG_SYS_INIT_RAM_LOCK
 187 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 188 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 189 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 190 /* The assembler doesn't like typecast */
 191 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 192         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 193           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 194 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 195
 196 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 197                                         GENERATED_GBL_DATA_SIZE)
 198 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 199
 200 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 201 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 202 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 203
 204 /* Serial Port - controlled on board with jumper J8
 205  * open - index 2
 206  * shorted - index 1
 207  */
 208 #define CONFIG_SYS_NS16550_SERIAL
 209 #define CONFIG_SYS_NS16550_REG_SIZE     1
 210 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
 211
 212 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
 213 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x11C600)
 214 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x11D500)
 215 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x11D600)
 216
 217 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 218
 219 /* I2C */
 220 /* QRIO GPIOs used for deblocking */
 221 #define KM_I2C_DEBLOCK_PORT     QRIO_GPIO_A
 222 #define KM_I2C_DEBLOCK_SCL      20
 223 #define KM_I2C_DEBLOCK_SDA      21
 224
 225 #define CONFIG_SYS_I2C
 226 #define CONFIG_SYS_I2C_INIT_BOARD
 227 #define CONFIG_SYS_I2C_SPEED            100000 /* deblocking */
 228 #define CONFIG_SYS_NUM_I2C_BUSES        3
 229 #define CONFIG_SYS_I2C_MAX_HOPS         1
 230 #define CONFIG_SYS_I2C_FSL              /* Use FSL I2C driver */
 231 #define CONFIG_I2C_MULTI_BUS
 232 #define CONFIG_I2C_CMD_TREE
 233 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 234 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 235 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 236 #define CONFIG_SYS_I2C_BUSES    {       {0, {I2C_NULL_HOP} }, \
 237                                         {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
 238                                         {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
 239                                 }
 240
 241 #define CONFIG_KM_IVM_BUS               1       /* I2C1 (Mux-Port 1)*/
 242
 243 /*
 244  * eSPI - Enhanced SPI
 245  */
 246
 247 /*
 248  * General PCI
 249  * Memory space is mapped 1-1, but I/O space must start from 0.
 250  */
 251
 252 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 253 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 254 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 255 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 256 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 257 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 258 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 259 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 260 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 261
 262 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 263 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 264 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 265 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 266 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 267 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8010000
 268 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 269 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8010000ull
 270 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 271
 272 /* Qman/Bman */
 273 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 274 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 275 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 276 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 277 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 278 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 279 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 280 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 281 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 282                                         CONFIG_SYS_BMAN_CENA_SIZE)
 283 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 284 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 285 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 286 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 287 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 288 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 289 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 290 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 291 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 292 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 293 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 294                                         CONFIG_SYS_QMAN_CENA_SIZE)
 295 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 296 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 297
 298 #define CONFIG_SYS_DPAA_FMAN
 299 #define CONFIG_SYS_DPAA_PME
 300 /* Default address of microcode for the Linux Fman driver
 301  * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
 302  * ucode is stored after env, so we got 0x120000.
 303  */
 304 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000
 305 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 306 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 307
 308 #define CONFIG_PCI_INDIRECT_BRIDGE
 309
 310 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 311
 312 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
 313 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x11
 314 #define CONFIG_SYS_TBIPA_VALUE  8
 315 #define CONFIG_ETHPRIME         "FM1@DTSEC5"
 316
 317 /*
 318  * Environment
 319  */
 320 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 321 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 322
 323 /*
 324  * Hardware Watchdog
 325  */
 326 #define CONFIG_WATCHDOG                 /* enable CPU watchdog */
 327 #define CONFIG_WATCHDOG_PRESC 34        /* wdog prescaler 2^(64-34) (~10min) */
 328 #define CONFIG_WATCHDOG_RC WRC_CHIP     /* reset chip on watchdog event */
 329
 330 /*
 331  * additionnal command line configuration.
 332  */
 333
 334 /*
 335  * For booting Linux, the board info and command line data
 336  * have to be in the first 64 MB of memory, since this is
 337  * the maximum mapped by the Linux kernel during initialization.
 338  */
 339 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 340 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 341
 342 #ifdef CONFIG_CMD_KGDB
 343 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 344 #endif
 345
 346 #define __USB_PHY_TYPE  utmi
 347 #define CONFIG_USB_EHCI_FSL
 348
 349 /*
 350  * Environment Configuration
 351  */
 352 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 353 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 354 #endif
 355
 356 /* architecture specific default bootargs */
 357 #define CONFIG_KM_DEF_BOOT_ARGS_CPU             ""
 358
 359 /* FIXME: FDT_ADDR is unspecified */
 360 #define CONFIG_KM_DEF_ENV_CPU                                           \
 361         "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"                   \
 362         "cramfsloadfdt="                                                \
 363                 "cramfsload ${fdt_addr_r} "                             \
 364                 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"             \
 365         "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0"              \
 366         "u-boot=" CONFIG_HOSTNAME "/u-boot.pbl\0"               \
 367         "update="                                                       \
 368                 "sf probe 0;sf erase 0 +${filesize};"                   \
 369                 "sf write ${load_addr_r} 0 ${filesize};\0"              \
 370         "set_fdthigh=true\0"                                            \
 371         "checkfdt=true\0"                                               \
 372         ""
 373
 374 #define CONFIG_HW_ENV_SETTINGS                                          \
 375         "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0"                       \
 376         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 377         "usb_dr_mode=host\0"
 378
 379 #define CONFIG_KM_NEW_ENV                                               \
 380         "newenv=sf probe 0;"                                            \
 381                 "sf erase " __stringify(CONFIG_ENV_OFFSET) " "          \
 382                 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
 383
 384 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
 385 #ifndef CONFIG_KM_DEF_ARCH
 386 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 387 #endif
 388
 389 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 390         CONFIG_KM_DEF_ENV                                               \
 391         CONFIG_KM_DEF_ARCH                                              \
 392         CONFIG_KM_NEW_ENV                                               \
 393         CONFIG_HW_ENV_SETTINGS                                          \
 394         "EEprom_ivm=pca9547:70:9\0"                                     \
 395         ""
 396
 397 /* App2 Local bus */
 398 #define CONFIG_SYS_LBAPP2_BASE          0xE0000000
 399 #define CONFIG_SYS_LBAPP2_BASE_PHYS     0xFE0000000ull
 400
 401 #define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \
 402                                 | BR_PS_8       /* Port Size 8 bits */ \
 403                                 | BR_DECC_OFF   /* no error corr */ \
 404                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 405                                 | BR_V)         /* valid */
 406
 407 #define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB        /* length 256MB */ \
 408                                 | OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
 409                                 | OR_GPCM_CSNT /* LCS 1/4 clk before */ \
 410                                 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
 411                                 | OR_GPCM_TRLX /* relaxed tmgs */ \
 412                                 | OR_GPCM_EAD) /* extra bus clk cycles */
 413 /* Local bus app2 Base Address */
 414 #define CONFIG_SYS_BR3_PRELIM  CONFIG_SYS_LBAPP2_BR_PRELIM
 415 /* Local bus app2 Options */
 416 #define CONFIG_SYS_OR3_PRELIM  CONFIG_SYS_LBAPP2_OR_PRELIM
 417
 418 #endif  /* __CONFIG_H */