1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2013 Keymile AG
4 * Valentin Longchamp <valentin.longchamp@keymile.com>
10 #if defined(CONFIG_KMCOGE4)
11 #define CONFIG_HOSTNAME "kmcoge4"
12 #define CONFIG_KM_BOARD_NAME "kmcoge4"
15 #error ("Board not supported")
18 #define CONFIG_KMP204X
20 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
22 /* an additionnal option is required for UBI as subpage access is
25 #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
27 #define CONFIG_NAND_ECC_BCH
29 /* common KM defines */
30 #include "km/keymile-common.h"
32 #define CONFIG_SYS_RAMBOOT
33 #define CONFIG_RAMBOOT_PBL
34 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
35 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
36 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
37 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
39 /* High Level Configuration Options */
40 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
41 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
43 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
44 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
45 #define CONFIG_PCIE1 /* PCIE controller 1 */
46 #define CONFIG_PCIE3 /* PCIE controller 3 */
47 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
48 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
50 #define CONFIG_SYS_DPAA_RMAN /* RMan */
52 /* Environment in SPI Flash */
53 #define CONFIG_ENV_TOTAL_SIZE 0x020000
56 unsigned long get_board_sys_clk(unsigned long dummy);
58 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
61 * These can be toggled for performance analysis, otherwise use default.
63 #define CONFIG_SYS_CACHE_STASHING
64 #define CONFIG_BACKSIDE_L2_CACHE
65 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
66 #define CONFIG_BTB /* toggle branch predition */
68 #define CONFIG_ENABLE_36BIT_PHYS
70 #define CONFIG_ADDR_MAP
71 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
73 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
76 * Config the L3 Cache as L3 SRAM
78 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
79 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
80 CONFIG_RAMBOOT_TEXT_BASE)
81 #define CONFIG_SYS_L3_SIZE (1024 << 10)
82 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
84 #define CONFIG_SYS_DCSRBAR 0xf0000000
85 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
90 #define CONFIG_VERY_BIG_RAM
91 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
92 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
94 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
95 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
97 #define CONFIG_DDR_SPD
99 #define CONFIG_SYS_SPD_BUS_NUM 0
100 #define SPD_EEPROM_ADDRESS 0x54
101 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
103 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
104 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
106 /******************************************************************************
108 * ... -------------------------------------------------------
109 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
110 * ... |<------------------- pram -------------------------->|
111 * ... -------------------------------------------------------
113 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
114 * @CONFIG_KM_PHRAM: address for /var
115 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
116 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
119 /* size of rootfs in RAM */
120 #define CONFIG_KM_ROOTFSSIZE 0x0
121 /* pseudo-non volatile RAM [hex] */
122 #define CONFIG_KM_PNVRAM 0x80000
123 /* physical RAM MTD size [hex] */
124 #define CONFIG_KM_PHRAM 0x100000
125 /* reserved pram area at the end of memory [hex]
126 * u-boot reserves some memory for the MP boot page
128 #define CONFIG_KM_RESERVED_PRAM 0x1000
129 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
130 * is not valid yet, which is the case for when u-boot copies itself to RAM
132 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
134 #define CONFIG_KM_CRAMFS_ADDR 0x2000000
135 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
136 #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */
139 * Local Bus Definitions
142 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
143 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2)
146 #define CONFIG_NAND_FSL_ELBC
147 #define CONFIG_SYS_NAND_BASE 0xffa00000
148 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
150 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
151 #define CONFIG_SYS_MAX_NAND_DEVICE 1
152 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
154 /* NAND flash config */
155 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
156 | BR_PS_8 /* Port Size = 8 bit */ \
157 | BR_MS_FCM /* MSEL = FCM */ \
160 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
161 | OR_FCM_BCTLD /* LBCTL not ass */ \
162 | OR_FCM_SCY_1 /* 1 clk wait cycle */ \
163 | OR_FCM_RST /* 1 clk read setup */ \
164 | OR_FCM_PGS /* Large page size */ \
165 | OR_FCM_CST) /* 0.25 command setup */
167 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
168 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
171 #define CONFIG_SYS_QRIO_BASE 0xfb000000
172 #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull
174 #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
175 | BR_PS_8 /* Port Size 8 bits */ \
176 | BR_DECC_OFF /* no error corr */ \
177 | BR_MS_GPCM /* MSEL = GPCM */ \
180 #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \
181 | OR_GPCM_BCTLD /* no LCTL assert */ \
182 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
183 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
184 | OR_GPCM_TRLX /* relaxed tmgs */ \
185 | OR_GPCM_EAD) /* extra bus clk cycles */
187 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
188 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
190 #define CONFIG_MISC_INIT_F
192 #define CONFIG_HWCONFIG
194 /* define to use L1 as initial stack */
195 #define CONFIG_L1_INIT_RAM
196 #define CONFIG_SYS_INIT_RAM_LOCK
197 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
198 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
199 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
200 /* The assembler doesn't like typecast */
201 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
202 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
203 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
204 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
206 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
207 GENERATED_GBL_DATA_SIZE)
208 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
210 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
211 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
212 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
214 /* Serial Port - controlled on board with jumper J8
218 #define CONFIG_SYS_NS16550_SERIAL
219 #define CONFIG_SYS_NS16550_REG_SIZE 1
220 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
222 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
223 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x11C600)
224 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x11D500)
225 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x11D600)
227 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
231 #define CONFIG_SYS_I2C
232 #define CONFIG_SYS_I2C_INIT_BOARD
233 #define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */
234 #define CONFIG_SYS_NUM_I2C_BUSES 3
235 #define CONFIG_SYS_I2C_MAX_HOPS 1
236 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */
237 #define CONFIG_I2C_MULTI_BUS
238 #define CONFIG_I2C_CMD_TREE
239 #define CONFIG_SYS_FSL_I2C_SPEED 400000
240 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
241 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
242 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
243 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
244 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
247 void set_sda(int state);
248 void set_scl(int state);
253 #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/
256 * eSPI - Enhanced SPI
261 * Memory space is mapped 1-1, but I/O space must start from 0.
264 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
265 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
266 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
267 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
268 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
269 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
270 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
271 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
272 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
274 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
275 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
276 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
277 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
278 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
279 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000
280 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
281 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull
282 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
285 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
286 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
287 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
288 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
289 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
290 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
291 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
292 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
293 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
294 CONFIG_SYS_BMAN_CENA_SIZE)
295 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
296 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
297 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
298 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
299 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
300 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
301 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
302 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
303 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
304 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
305 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
306 CONFIG_SYS_QMAN_CENA_SIZE)
307 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
308 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
310 #define CONFIG_SYS_DPAA_FMAN
311 #define CONFIG_SYS_DPAA_PME
312 /* Default address of microcode for the Linux Fman driver
313 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
314 * ucode is stored after env, so we got 0x120000.
316 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000
317 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
318 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
320 #define CONFIG_PHYLIB_10G
322 #define CONFIG_PCI_INDIRECT_BRIDGE
324 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
326 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
327 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
328 #define CONFIG_SYS_TBIPA_VALUE 8
329 #define CONFIG_ETHPRIME "FM1@DTSEC5"
334 #define CONFIG_LOADS_ECHO /* echo on for serial download */
335 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
340 #define CONFIG_WATCHDOG /* enable CPU watchdog */
341 #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */
342 #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
345 * additionnal command line configuration.
348 /* we don't need flash support */
349 #undef CONFIG_JFFS2_CMDLINE
352 * For booting Linux, the board info and command line data
353 * have to be in the first 64 MB of memory, since this is
354 * the maximum mapped by the Linux kernel during initialization.
356 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
357 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
359 #ifdef CONFIG_CMD_KGDB
360 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
363 #define __USB_PHY_TYPE utmi
364 #define CONFIG_USB_EHCI_FSL
367 * Environment Configuration
369 #define CONFIG_ENV_OVERWRITE
370 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
371 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
374 /* architecture specific default bootargs */
375 #define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
377 /* FIXME: FDT_ADDR is unspecified */
378 #define CONFIG_KM_DEF_ENV_CPU \
379 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
381 "cramfsload ${fdt_addr_r} " \
382 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
383 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
384 "u-boot=" CONFIG_HOSTNAME "/u-boot.pbl\0" \
386 "sf probe 0;sf erase 0 +${filesize};" \
387 "sf write ${load_addr_r} 0 ${filesize};\0" \
388 "set_fdthigh=true\0" \
392 #define CONFIG_HW_ENV_SETTINGS \
393 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
394 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
397 #define CONFIG_KM_NEW_ENV \
398 "newenv=sf probe 0;" \
399 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
400 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
402 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
403 #ifndef CONFIG_KM_DEF_ARCH
404 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
407 #define CONFIG_EXTRA_ENV_SETTINGS \
411 CONFIG_HW_ENV_SETTINGS \
412 "EEprom_ivm=pca9547:70:9\0" \
416 #define CONFIG_SYS_LBAPP2_BASE 0xE0000000
417 #define CONFIG_SYS_LBAPP2_BASE_PHYS 0xFE0000000ull
419 #define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \
420 | BR_PS_8 /* Port Size 8 bits */ \
421 | BR_DECC_OFF /* no error corr */ \
422 | BR_MS_GPCM /* MSEL = GPCM */ \
425 #define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB /* length 256MB */ \
426 | OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
427 | OR_GPCM_CSNT /* LCS 1/4 clk before */ \
428 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
429 | OR_GPCM_TRLX /* relaxed tmgs */ \
430 | OR_GPCM_EAD) /* extra bus clk cycles */
431 /* Local bus app2 Base Address */
432 #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM
433 /* Local bus app2 Options */
434 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM
436 #endif /* __CONFIG_H */