include/configs/kmeter1.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *                    Dave Liu <daveliu@freescale.com>
   4  *
   5  * Copyright (C) 2007 Logic Product Development, Inc.
   6  *                    Peter Barada <peterb@logicpd.com>
   7  *
   8  * Copyright (C) 2007 MontaVista Software, Inc.
   9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10  *
  11  * (C) Copyright 2008
  12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  */
  26 #define CONFIG_E300             1 /* E300 family */
  27 #define CONFIG_QE               1 /* Has QE */
  28 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  29 #define CONFIG_MPC8360          1 /* MPC8360 CPU specific */
  30 #define CONFIG_KMETER1          1 /* KMETER1 board specific */
  31 #define CONFIG_HOSTNAME         kmeter1
  32
  33 /* include common defines/options for all Keymile boards */
  34 #include "keymile-common.h"
  35
  36 #define CONFIG_MISC_INIT_R      1
  37 /*
  38  * System Clock Setup
  39  */
  40 #define CONFIG_83XX_CLKIN               66000000
  41 #define CONFIG_SYS_CLK_FREQ             66000000
  42 #define CONFIG_83XX_PCICLK              66000000
  43
  44 /*
  45  * Hardware Reset Configuration Word
  46  */
  47 #define CONFIG_SYS_HRCW_LOW (\
  48         HRCWL_CSB_TO_CLKIN_4X1 | \
  49         HRCWL_CORE_TO_CSB_2X1 | \
  50         HRCWL_CE_PLL_VCO_DIV_2 | \
  51         HRCWL_CE_TO_PLL_1X6 )
  52
  53 #define CONFIG_SYS_HRCW_HIGH (\
  54         HRCWH_CORE_ENABLE | \
  55         HRCWH_FROM_0X00000100 | \
  56         HRCWH_BOOTSEQ_DISABLE | \
  57         HRCWH_SW_WATCHDOG_DISABLE | \
  58         HRCWH_ROM_LOC_LOCAL_16BIT | \
  59         HRCWH_BIG_ENDIAN | \
  60         HRCWH_LALE_EARLY | \
  61         HRCWH_LDP_CLEAR )
  62
  63 /*
  64  * System IO Config
  65  */
  66 #define CONFIG_SYS_SICRH                0x00000006
  67 #define CONFIG_SYS_SICRL                0x00000000
  68
  69 /*
  70  * IMMR new address
  71  */
  72 #define CONFIG_SYS_IMMR         0xE0000000
  73
  74 /*
  75  * Bus Arbitration Configuration Register (ACR)
  76  */
  77 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  78 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  79 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  80 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  81
  82 /*
  83  * DDR Setup
  84  */
  85 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  86 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  87 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  88 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  89                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  90
  91 #define CFG_83XX_DDR_USES_CS0
  92
  93 #undef CONFIG_DDR_ECC
  94
  95 /*
  96  * DDRCDR - DDR Control Driver Register
  97  */
  98
  99 #undef CONFIG_SPD_EEPROM        /* Do not use SPD EEPROM for DDR setup */
 100
 101 /*
 102  * Manually set up DDR parameters
 103  */
 104 #define CONFIG_DDR_II
 105 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
 106 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 107 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 108                                          CSCONFIG_ROW_BIT_13 | \
 109                                          CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
 110
 111 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 112                                          SDRAM_CFG_SREN)
 113 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 114 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 115 #define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 116                                  (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
 117
 118 #define CONFIG_SYS_DDRCDR               0x40000001
 119 #define CONFIG_SYS_DDR_MODE             0x47860452
 120 #define CONFIG_SYS_DDR_MODE2            0x8080c000
 121
 122 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 123                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 124                                  (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 125                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 126                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 127                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 128                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 129                                  (0 << TIMING_CFG0_RWT_SHIFT))
 130
 131 #define CONFIG_SYS_DDR_TIMING_1 ((      TIMING_CFG1_CASLAT_50) | \
 132                                  ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
 133                                  ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 134                                  ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
 135                                  ( 7 << TIMING_CFG1_REFREC_SHIFT) | \
 136                                  ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 137                                  ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 138                                  ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
 139
 140 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 141                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 142                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 143                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 144                                  (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 145                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 146                                  (5 << TIMING_CFG2_CPO_SHIFT))
 147
 148 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 149
 150 /*
 151  * The reserved memory
 152  */
 153 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
 154 #define CONFIG_SYS_FLASH_BASE           0xF0000000
 155 #define CONFIG_SYS_FLASH_BASE_1         0xF2000000
 156 #define CONFIG_SYS_PIGGY_BASE           0xE8000000
 157 #define CONFIG_SYS_PIGGY_SIZE           128
 158 #define CONFIG_SYS_PAXE_BASE            0xA0000000
 159 #define CONFIG_SYS_PAXE_SIZE            512
 160
 161 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 162 #define CONFIG_SYS_RAMBOOT
 163 #else
 164 #undef  CONFIG_SYS_RAMBOOT
 165 #endif
 166
 167 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024) /* Reserve 384 kB for Mon */
 168
 169 /*
 170  * Initial RAM Base Address Setup
 171  */
 172 #define CONFIG_SYS_INIT_RAM_LOCK        1
 173 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 174 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
 175 #define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
 176 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 177
 178 /*
 179  * Local Bus Configuration & Clock Setup
 180  */
 181 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 182 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_2
 183 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 184
 185 /*
 186  * Init Local Bus Memory Controller:
 187  *
 188  * Bank Bus     Machine PortSz  Size  Device
 189  * ---- ---     ------- ------  -----  ------
 190  *  0   Local   GPCM    16 bit  256MB FLASH
 191  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 192  *  3   Local   GPCM     8 bit  512MB PAXE
 193  *
 194  */
 195 /*
 196  * FLASH on the Local Bus
 197  */
 198 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 199 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 200 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 201 #define CONFIG_SYS_FLASH_PROTECTION     1
 202 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 203
 204 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE /* Window base at flash base */
 205 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x8000001b /* 256MB window size */
 206
 207 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 208                                 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 209                                 BR_V)
 210
 211 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 212                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 213                                 OR_GPCM_SCY_5 | \
 214                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 215
 216 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of flash banks       */
 217 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
 218 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
 219
 220 #undef  CONFIG_SYS_FLASH_CHECKSUM
 221
 222 /*
 223  * PRIO1/PIGGY on the local bus CS1
 224  */
 225 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
 226 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000001A /* 128MB window size */
 227
 228 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_PIGGY_BASE | \
 229                                 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 230                                 BR_V)
 231 #define CONFIG_SYS_OR1_PRELIM           (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \
 232                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 233                                 OR_GPCM_SCY_2 | \
 234                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 235
 236 /*
 237  * PAXE on the local bus CS3
 238  */
 239 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PAXE_BASE /* Window base at flash base */
 240 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000001C /* 512MB window size */
 241
 242 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_PAXE_BASE | \
 243                                 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 244                                 BR_V)
 245 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
 246                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 247                                 OR_GPCM_SCY_2 | \
 248                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 249
 250 /*
 251  * Serial Port
 252  */
 253 #define CONFIG_CONS_INDEX       1
 254 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 255 #define CONFIG_SYS_NS16550
 256 #define CONFIG_SYS_NS16550_SERIAL
 257 #define CONFIG_SYS_NS16550_REG_SIZE     1
 258 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 259
 260 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 261 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 262
 263 /* Pass open firmware flat tree */
 264 #define CONFIG_OF_LIBFDT        1
 265 #define CONFIG_OF_BOARD_SETUP   1
 266 #define CONFIG_OF_STDOUT_VIA_ALIAS
 267
 268 /*
 269  * General PCI
 270  * Addresses are mapped 1-1.
 271  */
 272 #undef CONFIG_PCI               /* No PCI */
 273
 274 #ifndef CONFIG_NET_MULTI
 275 #define CONFIG_NET_MULTI        1
 276 #endif
 277 /*
 278  * QE UEC ethernet configuration
 279  */
 280 #define CONFIG_UEC_ETH
 281 #define CONFIG_ETHPRIME         "FSL UEC0"
 282
 283 #define CONFIG_UEC_ETH1         /* GETH1 */
 284 #define UEC_VERBOSE_DEBUG       1
 285
 286 #ifdef CONFIG_UEC_ETH1
 287 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 288 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE     /* not used in RMII Mode */
 289 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 290 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 291 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 292 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
 293 #endif
 294
 295 /*
 296  * Environment
 297  */
 298
 299 #ifndef CONFIG_SYS_RAMBOOT
 300 #define CONFIG_ENV_IS_IN_FLASH  1
 301 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 302 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 303 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 304
 305 /* Address and size of Redundant Environment Sector     */
 306 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 307 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 308
 309 #else /* CFG_RAMBOOT */
 310 #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 311 #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 312 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 313 #define CONFIG_ENV_SIZE         0x2000
 314 #endif /* CFG_RAMBOOT */
 315
 316 /* I2C */
 317 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 318 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 319 #define CONFIG_FSL_I2C
 320 #define CONFIG_SYS_I2C_SPEED    200000  /* I2C speed and slave address */
 321 #define CONFIG_SYS_I2C_SLAVE    0x7F
 322 #define CONFIG_SYS_I2C_OFFSET   0x3000
 323 #define CONFIG_I2C_MULTI_BUS    1
 324 #define CONFIG_I2C_MUX          1
 325
 326 /* EEprom support */
 327 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 328
 329 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 330 #define CONFIG_DTT_LM75         1       /* ON Semi's LM75               */
 331 #define CONFIG_DTT_SENSORS      {0, 1, 2, 3}    /* Sensor addresses             */
 332 #define CONFIG_SYS_DTT_MAX_TEMP 70
 333 #define CONFIG_SYS_DTT_LOW_TEMP -30
 334 #define CONFIG_SYS_DTT_HYSTERESIS       3
 335 #define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
 336
 337 #if defined(CONFIG_CMD_NAND)
 338 #define CONFIG_NAND_KMETER1
 339 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 340 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_PIGGY_BASE
 341 #endif
 342
 343 #if defined(CONFIG_PCI)
 344 #define CONFIG_CMD_PCI
 345 #endif
 346
 347 #if defined(CFG_RAMBOOT)
 348 #undef CONFIG_CMD_SAVEENV
 349 #undef CONFIG_CMD_LOADS
 350 #endif
 351
 352 /*
 353  * For booting Linux, the board info and command line data
 354  * have to be in the first 8 MB of memory, since this is
 355  * the maximum mapped by the Linux kernel during initialization.
 356  */
 357 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 358
 359 /*
 360  * Core HID Setup
 361  */
 362 #define CONFIG_SYS_HID0_INIT            0x000000000
 363 #define CONFIG_SYS_HID0_FINAL           HID0_ENABLE_MACHINE_CHECK
 364 #define CONFIG_SYS_HID2                 HID2_HBE
 365
 366 /*
 367  * MMU Setup
 368  */
 369
 370 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 371
 372 /* DDR: cache cacheable */
 373 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
 374                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 375 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 376 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 377 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 378
 379 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 380 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
 381                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 382 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
 383 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 384 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 385
 386 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 387 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 388 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
 389 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
 390                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 391 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 392
 393 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 394 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 395 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 396 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 397                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 398 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 399
 400 /* Stack in dcache: cacheable, no memory coherence */
 401 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 402 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 403 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 404 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 405
 406 /* PAXE:  icache cacheable, but dcache-inhibit and guarded */
 407 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 408 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 409 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
 410                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 411 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 412
 413 #ifdef CONFIG_PCI
 414 /* PCI MEM space: cacheable */
 415 #define CFG_IBAT6L      (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 416 #define CFG_IBAT6U      (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 417 #define CFG_DBAT6L      CFG_IBAT6L
 418 #define CFG_DBAT6U      CFG_IBAT6U
 419 /* PCI MMIO space: cache-inhibit and guarded */
 420 #define CFG_IBAT7L      (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
 421                          BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 422 #define CFG_IBAT7U      (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 423 #define CFG_DBAT7L      CFG_IBAT7L
 424 #define CFG_DBAT7U      CFG_IBAT7U
 425 #else /* CONFIG_PCI */
 426 #define CONFIG_SYS_IBAT6L       (0)
 427 #define CONFIG_SYS_IBAT6U       (0)
 428 #define CONFIG_SYS_IBAT7L       (0)
 429 #define CONFIG_SYS_IBAT7U       (0)
 430 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 431 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 432 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 433 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 434 #endif /* CONFIG_PCI */
 435
 436 /*
 437  * Internal Definitions
 438  *
 439  * Boot Flags
 440  */
 441 #define BOOTFLAG_COLD   0x01 /* Normal Power-On: Boot from FLASH */
 442 #define BOOTFLAG_WARM   0x02 /* Software reboot */
 443
 444 #define BOOTFLASH_START F0000000
 445
 446 #define CONFIG_PRAM     512     /* protected RAM [KBytes] */
 447
 448 #define MTDIDS_DEFAULT          "nor2=app"
 449 #define MTDPARTS_DEFAULT \
 450         "mtdparts=app:256k(u-boot),128k(env),128k(envred),"     \
 451         "1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)"
 452
 453 /*
 454  * Environment Configuration
 455  */
 456 #define CONFIG_ENV_OVERWRITE
 457 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 458 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 459 #endif
 460
 461 #define CONFIG_EXTRA_ENV_SETTINGS \
 462        CONFIG_KM_DEF_ENV                                                \
 463         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
 464         "addcon=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 465         "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0"                     \
 466         "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0"              \
 467         "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0"                      \
 468         "loadkernel=tftp ${kernel_addr_r} ${bootfile}\0"                \
 469         "unlock=yes\0"                                                  \
 470         "fdt_addr=F0080000\0"                                           \
 471         "kernel_addr=F00a0000\0"                                        \
 472         "ramdisk_addr=F03a0000\0"                                       \
 473         "ramdisk_addr_r=F10000\0"                                       \
 474         "EEprom_ivm=pca9547:70:9\0"                                     \
 475         "dtt_bus=pca9547:70:a\0"                                        \
 476         "mtdids=nor0=app \0"                                            \
 477         "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0"                       \
 478    ""
 479
 480 #if defined(CONFIG_UEC_ETH)
 481 #define CONFIG_HAS_ETH0
 482 #endif
 483
 484 #endif /* __CONFIG_H */