include/configs/kmeter1.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *                    Dave Liu <daveliu@freescale.com>
   4  *
   5  * Copyright (C) 2007 Logic Product Development, Inc.
   6  *                    Peter Barada <peterb@logicpd.com>
   7  *
   8  * Copyright (C) 2007 MontaVista Software, Inc.
   9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10  *
  11  * (C) Copyright 2008
  12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  */
  26 #define CONFIG_E300             1 /* E300 family */
  27 #define CONFIG_QE               1 /* Has QE */
  28 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  29 #define CONFIG_MPC8360          1 /* MPC8360 CPU specific */
  30 #define CONFIG_KMETER1          1 /* KMETER1 board specific */
  31 #define CONFIG_HOSTNAME         kmeter1
  32
  33 /* include common defines/options for all Keymile boards */
  34 #include "keymile-common.h"
  35
  36 #define MTDIDS_DEFAULT          "nor0=boot"
  37 #define MTDPARTS_DEFAULT        \
  38         "mtdparts=boot:768k(u-boot),128k(env),128k(envred),"    \
  39         "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
  40
  41 #define CONFIG_MISC_INIT_R      1
  42 /*
  43  * System Clock Setup
  44  */
  45 #define CONFIG_83XX_CLKIN               66000000
  46 #define CONFIG_SYS_CLK_FREQ             66000000
  47 #define CONFIG_83XX_PCICLK              66000000
  48
  49 /*
  50  * Hardware Reset Configuration Word
  51  */
  52 #define CONFIG_SYS_HRCW_LOW (\
  53         HRCWL_CSB_TO_CLKIN_4X1 | \
  54         HRCWL_CORE_TO_CSB_2X1 | \
  55         HRCWL_CE_PLL_VCO_DIV_2 | \
  56         HRCWL_CE_TO_PLL_1X6 )
  57
  58 #define CONFIG_SYS_HRCW_HIGH (\
  59         HRCWH_CORE_ENABLE | \
  60         HRCWH_FROM_0X00000100 | \
  61         HRCWH_BOOTSEQ_DISABLE | \
  62         HRCWH_SW_WATCHDOG_DISABLE | \
  63         HRCWH_ROM_LOC_LOCAL_16BIT | \
  64         HRCWH_BIG_ENDIAN | \
  65         HRCWH_LALE_EARLY | \
  66         HRCWH_LDP_CLEAR )
  67
  68 /*
  69  * System IO Config
  70  */
  71 #define CONFIG_SYS_SICRH                0x00000006
  72 #define CONFIG_SYS_SICRL                0x00000000
  73
  74 /*
  75  * IMMR new address
  76  */
  77 #define CONFIG_SYS_IMMR         0xE0000000
  78
  79 /*
  80  * Bus Arbitration Configuration Register (ACR)
  81  */
  82 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  83 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  84 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  85 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  86
  87 /*
  88  * DDR Setup
  89  */
  90 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  91 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  92 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  93 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  94                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  95
  96 #define CFG_83XX_DDR_USES_CS0
  97
  98 #undef CONFIG_DDR_ECC
  99
 100 /*
 101  * DDRCDR - DDR Control Driver Register
 102  */
 103
 104 #undef CONFIG_SPD_EEPROM        /* Do not use SPD EEPROM for DDR setup */
 105
 106 /*
 107  * Manually set up DDR parameters
 108  */
 109 #define CONFIG_DDR_II
 110 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
 111 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 112 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 113                                          CSCONFIG_ROW_BIT_13 | \
 114                                          CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
 115
 116 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 117                                          SDRAM_CFG_SREN)
 118 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 119 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 120 #define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 121                                  (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
 122
 123 #define CONFIG_SYS_DDRCDR               0x40000001
 124 #define CONFIG_SYS_DDR_MODE             0x47860452
 125 #define CONFIG_SYS_DDR_MODE2            0x8080c000
 126
 127 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 128                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 129                                  (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 130                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 131                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 132                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 133                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 134                                  (0 << TIMING_CFG0_RWT_SHIFT))
 135
 136 #define CONFIG_SYS_DDR_TIMING_1 ((      TIMING_CFG1_CASLAT_50) | \
 137                                  ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
 138                                  ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 139                                  ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
 140                                  ( 7 << TIMING_CFG1_REFREC_SHIFT) | \
 141                                  ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 142                                  ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 143                                  ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
 144
 145 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 146                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 147                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 148                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 149                                  (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 150                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 151                                  (5 << TIMING_CFG2_CPO_SHIFT))
 152
 153 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 154
 155 /*
 156  * The reserved memory
 157  */
 158 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
 159 #define CONFIG_SYS_FLASH_BASE           0xF0000000
 160 #define CONFIG_SYS_PIGGY_BASE           0xE8000000
 161 #define CONFIG_SYS_PIGGY_SIZE           128
 162 #define CONFIG_SYS_PAXE_BASE            0xA0000000
 163 #define CONFIG_SYS_PAXE_SIZE            512
 164
 165 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 166 #define CONFIG_SYS_RAMBOOT
 167 #else
 168 #undef  CONFIG_SYS_RAMBOOT
 169 #endif
 170
 171 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024) /* Reserve 384 kB for Mon */
 172
 173 /*
 174  * Initial RAM Base Address Setup
 175  */
 176 #define CONFIG_SYS_INIT_RAM_LOCK        1
 177 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 178 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
 179 #define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
 180 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 181
 182 /*
 183  * Local Bus Configuration & Clock Setup
 184  */
 185 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 186 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_2
 187 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 188
 189 /*
 190  * Init Local Bus Memory Controller:
 191  *
 192  * Bank Bus     Machine PortSz  Size  Device
 193  * ---- ---     ------- ------  -----  ------
 194  *  0   Local   GPCM    16 bit  256MB FLASH
 195  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 196  *  3   Local   GPCM     8 bit  512MB PAXE
 197  *
 198  */
 199 /*
 200  * FLASH on the Local Bus
 201  */
 202 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 203 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 204 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 205 #define CONFIG_SYS_FLASH_PROTECTION     1
 206 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 207
 208 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE /* Window base at flash base */
 209 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x8000001b /* 256MB window size */
 210
 211 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 212                                 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 213                                 BR_V)
 214
 215 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 216                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 217                                 OR_GPCM_SCY_5 | \
 218                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 219
 220 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks       */
 221 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
 222 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 223
 224 #undef  CONFIG_SYS_FLASH_CHECKSUM
 225
 226 /*
 227  * PRIO1/PIGGY on the local bus CS1
 228  */
 229 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
 230 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000001A /* 128MB window size */
 231
 232 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_PIGGY_BASE | \
 233                                 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 234                                 BR_V)
 235 #define CONFIG_SYS_OR1_PRELIM           (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \
 236                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 237                                 OR_GPCM_SCY_2 | \
 238                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 239
 240 /*
 241  * PAXE on the local bus CS3
 242  */
 243 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PAXE_BASE /* Window base at flash base */
 244 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000001C /* 512MB window size */
 245
 246 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_PAXE_BASE | \
 247                                 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 248                                 BR_V)
 249 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
 250                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 251                                 OR_GPCM_SCY_2 | \
 252                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 253
 254 /*
 255  * Serial Port
 256  */
 257 #define CONFIG_CONS_INDEX       1
 258 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 259 #define CONFIG_SYS_NS16550
 260 #define CONFIG_SYS_NS16550_SERIAL
 261 #define CONFIG_SYS_NS16550_REG_SIZE     1
 262 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 263
 264 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 265 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 266
 267 /* Pass open firmware flat tree */
 268 #define CONFIG_OF_LIBFDT        1
 269 #define CONFIG_OF_BOARD_SETUP   1
 270 #define CONFIG_OF_STDOUT_VIA_ALIAS
 271
 272 /*
 273  * General PCI
 274  * Addresses are mapped 1-1.
 275  */
 276 #undef CONFIG_PCI               /* No PCI */
 277
 278 #ifndef CONFIG_NET_MULTI
 279 #define CONFIG_NET_MULTI        1
 280 #endif
 281 /*
 282  * QE UEC ethernet configuration
 283  */
 284 #define CONFIG_UEC_ETH
 285 #define CONFIG_ETHPRIME         "FSL UEC0"
 286
 287 #define CONFIG_UEC_ETH1         /* GETH1 */
 288 #define UEC_VERBOSE_DEBUG       1
 289
 290 #ifdef CONFIG_UEC_ETH1
 291 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 292 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE     /* not used in RMII Mode */
 293 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 294 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 295 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 296 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
 297 #endif
 298
 299 /*
 300  * Environment
 301  */
 302
 303 #ifndef CONFIG_SYS_RAMBOOT
 304 #define CONFIG_ENV_IS_IN_FLASH  1
 305 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 306 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 307 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 308
 309 /* Address and size of Redundant Environment Sector     */
 310 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 311 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 312
 313 #else /* CFG_RAMBOOT */
 314 #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 315 #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 316 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 317 #define CONFIG_ENV_SIZE         0x2000
 318 #endif /* CFG_RAMBOOT */
 319
 320 /* I2C */
 321 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 322 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 323 #define CONFIG_FSL_I2C
 324 #define CONFIG_SYS_I2C_SPEED    200000  /* I2C speed and slave address */
 325 #define CONFIG_SYS_I2C_SLAVE    0x7F
 326 #define CONFIG_SYS_I2C_OFFSET   0x3000
 327 #define CONFIG_I2C_MULTI_BUS    1
 328 #define CONFIG_I2C_MUX          1
 329
 330 /* EEprom support */
 331 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 332
 333 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 334 #define CONFIG_DTT_LM75         1       /* ON Semi's LM75               */
 335 #define CONFIG_DTT_SENSORS      {0, 1, 2, 3}    /* Sensor addresses             */
 336 #define CONFIG_SYS_DTT_MAX_TEMP 70
 337 #define CONFIG_SYS_DTT_LOW_TEMP -30
 338 #define CONFIG_SYS_DTT_HYSTERESIS       3
 339 #define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
 340
 341 #if defined(CONFIG_CMD_NAND)
 342 #define CONFIG_NAND_KMETER1
 343 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 344 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_PIGGY_BASE
 345 #endif
 346
 347 #if defined(CONFIG_PCI)
 348 #define CONFIG_CMD_PCI
 349 #endif
 350
 351 #if defined(CFG_RAMBOOT)
 352 #undef CONFIG_CMD_SAVEENV
 353 #undef CONFIG_CMD_LOADS
 354 #endif
 355
 356 /*
 357  * For booting Linux, the board info and command line data
 358  * have to be in the first 8 MB of memory, since this is
 359  * the maximum mapped by the Linux kernel during initialization.
 360  */
 361 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 362
 363 /*
 364  * Core HID Setup
 365  */
 366 #define CONFIG_SYS_HID0_INIT            0x000000000
 367 #define CONFIG_SYS_HID0_FINAL           HID0_ENABLE_MACHINE_CHECK
 368 #define CONFIG_SYS_HID2                 HID2_HBE
 369
 370 /*
 371  * MMU Setup
 372  */
 373
 374 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 375
 376 /* DDR: cache cacheable */
 377 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
 378                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 379 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 380 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 381 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 382
 383 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 384 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
 385                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 386 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
 387 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 388 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 389
 390 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 391 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 392 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
 393 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
 394                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 395 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 396
 397 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 398 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 399 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 400 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 401                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 402 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 403
 404 /* Stack in dcache: cacheable, no memory coherence */
 405 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 406 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 407 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 408 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 409
 410 /* PAXE:  icache cacheable, but dcache-inhibit and guarded */
 411 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 412 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 413 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
 414                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 415 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 416
 417 #ifdef CONFIG_PCI
 418 /* PCI MEM space: cacheable */
 419 #define CFG_IBAT6L      (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 420 #define CFG_IBAT6U      (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 421 #define CFG_DBAT6L      CFG_IBAT6L
 422 #define CFG_DBAT6U      CFG_IBAT6U
 423 /* PCI MMIO space: cache-inhibit and guarded */
 424 #define CFG_IBAT7L      (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
 425                          BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 426 #define CFG_IBAT7U      (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 427 #define CFG_DBAT7L      CFG_IBAT7L
 428 #define CFG_DBAT7U      CFG_IBAT7U
 429 #else /* CONFIG_PCI */
 430 #define CONFIG_SYS_IBAT6L       (0)
 431 #define CONFIG_SYS_IBAT6U       (0)
 432 #define CONFIG_SYS_IBAT7L       (0)
 433 #define CONFIG_SYS_IBAT7U       (0)
 434 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 435 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 436 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 437 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 438 #endif /* CONFIG_PCI */
 439
 440 /*
 441  * Internal Definitions
 442  *
 443  * Boot Flags
 444  */
 445 #define BOOTFLAG_COLD   0x01 /* Normal Power-On: Boot from FLASH */
 446 #define BOOTFLAG_WARM   0x02 /* Software reboot */
 447
 448 #define BOOTFLASH_START F0000000
 449
 450 #define CONFIG_PRAM     512     /* protected RAM [KBytes] */
 451
 452 #define MTDIDS_DEFAULT          "nor2=app"
 453 #define MTDPARTS_DEFAULT \
 454         "mtdparts=app:256k(u-boot),128k(env),128k(envred),"     \
 455         "1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)"
 456
 457 /*
 458  * Environment Configuration
 459  */
 460 #define CONFIG_ENV_OVERWRITE
 461 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 462 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 463 #endif
 464
 465 #define CONFIG_EXTRA_ENV_SETTINGS \
 466        CONFIG_KM_DEF_ENV                                                \
 467         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
 468         "addcon=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 469         "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0"                     \
 470         "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0"              \
 471         "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0"                      \
 472         "loadkernel=tftp ${kernel_addr_r} ${bootfile}\0"                \
 473         "unlock=yes\0"                                                  \
 474         "fdt_addr=F0080000\0"                                           \
 475         "kernel_addr=F00a0000\0"                                        \
 476         "ramdisk_addr=F03a0000\0"                                       \
 477         "ramdisk_addr_r=F10000\0"                                       \
 478         "EEprom_ivm=pca9547:70:9\0"                                     \
 479         "dtt_bus=pca9547:70:a\0"                                        \
 480         "mtdids=nor0=app \0"                                            \
 481         "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0"                       \
 482    ""
 483
 484 #if defined(CONFIG_UEC_ETH)
 485 #define CONFIG_HAS_ETH0
 486 #endif
 487
 488 #endif /* __CONFIG_H */