tizen: fix to load kernel image with partition information
[profile/mobile/platform/kernel/u-boot-tm1.git] / include / configs / kmeter1.h
1 /*
2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
3  *                    Dave Liu <daveliu@freescale.com>
4  *
5  * Copyright (C) 2007 Logic Product Development, Inc.
6  *                    Peter Barada <peterb@logicpd.com>
7  *
8  * Copyright (C) 2007 MontaVista Software, Inc.
9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
10  *
11  * (C) Copyright 2008
12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
13  *
14  * This program is free software; you can redistribute it and/or
15  * modify it under the terms of the GNU General Public License as
16  * published by the Free Software Foundation; either version 2 of
17  * the License, or (at your option) any later version.
18  */
19
20 #ifndef __CONFIG_H
21 #define __CONFIG_H
22
23 /*
24  * High Level Configuration Options
25  */
26 #define CONFIG_E300             1 /* E300 family */
27 #define CONFIG_QE               1 /* Has QE */
28 #define CONFIG_MPC83xx          1 /* MPC83xx family */
29 #define CONFIG_MPC8360          1 /* MPC8360 CPU specific */
30 #define CONFIG_KMETER1          1 /* KMETER1 board specific */
31 #define CONFIG_HOSTNAME         kmeter1
32
33 #define CONFIG_SYS_TEXT_BASE    0xF0000000
34
35 /* include common defines/options for all Keymile boards */
36 #include "keymile-common.h"
37
38 #define CONFIG_KM_UBI_PARTITION_NAME    "ubi0"
39
40 #define MTDIDS_DEFAULT          "nor0=boot"
41 #define MTDPARTS_DEFAULT        \
42         "mtdparts=boot:768k(u-boot),128k(env),128k(envred),"    \
43         "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
44
45 #define CONFIG_MISC_INIT_R      1
46 /*
47  * System Clock Setup
48  */
49 #define CONFIG_83XX_CLKIN               66000000
50 #define CONFIG_SYS_CLK_FREQ             66000000
51 #define CONFIG_83XX_PCICLK              66000000
52
53 /*
54  * Hardware Reset Configuration Word
55  */
56 #define CONFIG_SYS_HRCW_LOW (\
57         HRCWL_CSB_TO_CLKIN_4X1 | \
58         HRCWL_CORE_TO_CSB_2X1 | \
59         HRCWL_CE_PLL_VCO_DIV_2 | \
60         HRCWL_CE_TO_PLL_1X6 )
61
62 #define CONFIG_SYS_HRCW_HIGH (\
63         HRCWH_CORE_ENABLE | \
64         HRCWH_FROM_0X00000100 | \
65         HRCWH_BOOTSEQ_DISABLE | \
66         HRCWH_SW_WATCHDOG_DISABLE | \
67         HRCWH_ROM_LOC_LOCAL_16BIT | \
68         HRCWH_BIG_ENDIAN | \
69         HRCWH_LALE_EARLY | \
70         HRCWH_LDP_CLEAR )
71
72 /*
73  * System IO Config
74  */
75 #define CONFIG_SYS_SICRH                0x00000006
76 #define CONFIG_SYS_SICRL                0x00000000
77
78 /*
79  * IMMR new address
80  */
81 #define CONFIG_SYS_IMMR         0xE0000000
82
83 /*
84  * Bus Arbitration Configuration Register (ACR)
85  */
86 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
87 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
88 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
89 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
90
91 /*
92  * DDR Setup
93  */
94 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
95 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
96 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
97 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
98                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
99
100 #define CFG_83XX_DDR_USES_CS0
101
102 #undef CONFIG_DDR_ECC
103
104 /*
105  * DDRCDR - DDR Control Driver Register
106  */
107
108 #undef CONFIG_SPD_EEPROM        /* Do not use SPD EEPROM for DDR setup */
109
110 /*
111  * Manually set up DDR parameters
112  */
113 #define CONFIG_DDR_II
114 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
115 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
116 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
117                                          CSCONFIG_ROW_BIT_13 | \
118                                          CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
119
120 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
121                                          SDRAM_CFG_SREN)
122 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
123 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
124 #define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
125                                  (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
126
127 #define CONFIG_SYS_DDRCDR               0x40000001
128 #define CONFIG_SYS_DDR_MODE             0x47860452
129 #define CONFIG_SYS_DDR_MODE2            0x8080c000
130
131 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
132                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
133                                  (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
134                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
135                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
136                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
137                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
138                                  (0 << TIMING_CFG0_RWT_SHIFT))
139
140 #define CONFIG_SYS_DDR_TIMING_1 ((      TIMING_CFG1_CASLAT_50) | \
141                                  ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
142                                  ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
143                                  ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
144                                  ( 7 << TIMING_CFG1_REFREC_SHIFT) | \
145                                  ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
146                                  ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
147                                  ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
148
149 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
150                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
151                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
152                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
153                                  (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
154                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
155                                  (5 << TIMING_CFG2_CPO_SHIFT))
156
157 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
158
159 /*
160  * The reserved memory
161  */
162 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
163 #define CONFIG_SYS_FLASH_BASE           0xF0000000
164 #define CONFIG_SYS_PIGGY_BASE           0xE8000000
165 #define CONFIG_SYS_PIGGY_SIZE           128
166 #define CONFIG_SYS_PAXE_BASE            0xA0000000
167 #define CONFIG_SYS_PAXE_SIZE            512
168
169 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
170 #define CONFIG_SYS_RAMBOOT
171 #else
172 #undef  CONFIG_SYS_RAMBOOT
173 #endif
174
175 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024) /* Reserve 384 kB for Mon */
176
177 /*
178  * Initial RAM Base Address Setup
179  */
180 #define CONFIG_SYS_INIT_RAM_LOCK        1
181 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
182 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
183 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
184
185 /*
186  * Local Bus Configuration & Clock Setup
187  */
188 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
189 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_2
190 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
191
192 /*
193  * Init Local Bus Memory Controller:
194  *
195  * Bank Bus     Machine PortSz  Size  Device
196  * ---- ---     ------- ------  -----  ------
197  *  0   Local   GPCM    16 bit  256MB FLASH
198  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
199  *  3   Local   GPCM     8 bit  512MB PAXE
200  *
201  */
202 /*
203  * FLASH on the Local Bus
204  */
205 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
206 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
207 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
208 #define CONFIG_SYS_FLASH_PROTECTION     1
209 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
210
211 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE /* Window base at flash base */
212 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x8000001b /* 256MB window size */
213
214 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
215                                 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
216                                 BR_V)
217
218 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
219                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
220                                 OR_GPCM_SCY_5 | \
221                                 OR_GPCM_TRLX | OR_GPCM_EAD)
222
223 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks       */
224 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
225 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
226
227 #undef  CONFIG_SYS_FLASH_CHECKSUM
228
229 /*
230  * PRIO1/PIGGY on the local bus CS1
231  */
232 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
233 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000001A /* 128MB window size */
234
235 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_PIGGY_BASE | \
236                                 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
237                                 BR_V)
238 #define CONFIG_SYS_OR1_PRELIM           (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \
239                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
240                                 OR_GPCM_SCY_2 | \
241                                 OR_GPCM_TRLX | OR_GPCM_EAD)
242
243 /*
244  * PAXE on the local bus CS3
245  */
246 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PAXE_BASE /* Window base at flash base */
247 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000001C /* 512MB window size */
248
249 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_PAXE_BASE | \
250                                 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
251                                 BR_V)
252 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
253                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
254                                 OR_GPCM_SCY_2 | \
255                                 OR_GPCM_TRLX | OR_GPCM_EAD)
256
257 /*
258  * Serial Port
259  */
260 #define CONFIG_CONS_INDEX       1
261 #define CONFIG_SYS_NS16550
262 #define CONFIG_SYS_NS16550_SERIAL
263 #define CONFIG_SYS_NS16550_REG_SIZE     1
264 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
265
266 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
267 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
268
269 /* Pass open firmware flat tree */
270 #define CONFIG_OF_LIBFDT        1
271 #define CONFIG_OF_BOARD_SETUP   1
272 #define CONFIG_OF_STDOUT_VIA_ALIAS
273
274 /*
275  * General PCI
276  * Addresses are mapped 1-1.
277  */
278 #undef CONFIG_PCI               /* No PCI */
279
280 #ifndef CONFIG_NET_MULTI
281 #define CONFIG_NET_MULTI        1
282 #endif
283 /*
284  * QE UEC ethernet configuration
285  */
286 #define CONFIG_UEC_ETH
287 #define CONFIG_ETHPRIME         "UEC0"
288
289 #define CONFIG_UEC_ETH1         /* GETH1 */
290 #define UEC_VERBOSE_DEBUG       1
291
292 #ifdef CONFIG_UEC_ETH1
293 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
294 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE     /* not used in RMII Mode */
295 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
296 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
297 #define CONFIG_SYS_UEC1_PHY_ADDR        0
298 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
299 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
300 #endif
301
302 /*
303  * Environment
304  */
305
306 #ifndef CONFIG_SYS_RAMBOOT
307 #define CONFIG_ENV_IS_IN_FLASH  1
308 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
309 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
310 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
311
312 /* Address and size of Redundant Environment Sector     */
313 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
314 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
315
316 #else /* CFG_RAMBOOT */
317 #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
318 #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
319 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
320 #define CONFIG_ENV_SIZE         0x2000
321 #endif /* CFG_RAMBOOT */
322
323 /* I2C */
324 #define CONFIG_HARD_I2C         /* I2C with hardware support */
325 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
326 #define CONFIG_FSL_I2C
327 #define CONFIG_SYS_I2C_SPEED    200000  /* I2C speed and slave address */
328 #define CONFIG_SYS_I2C_SLAVE    0x7F
329 #define CONFIG_SYS_I2C_OFFSET   0x3000
330 #define CONFIG_I2C_MULTI_BUS    1
331 #define CONFIG_I2C_MUX          1
332
333 /* EEprom support */
334 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
335
336 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
337 #define CONFIG_DTT_LM75         1       /* ON Semi's LM75               */
338 #define CONFIG_DTT_SENSORS      {0, 1, 2, 3}    /* Sensor addresses             */
339 #define CONFIG_SYS_DTT_MAX_TEMP 70
340 #define CONFIG_SYS_DTT_LOW_TEMP -30
341 #define CONFIG_SYS_DTT_HYSTERESIS       3
342 #define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
343
344 #if defined(CONFIG_CMD_NAND)
345 #define CONFIG_NAND_KMETER1
346 #define CONFIG_SYS_MAX_NAND_DEVICE      1
347 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_PIGGY_BASE
348 #endif
349
350 #if defined(CONFIG_PCI)
351 #define CONFIG_CMD_PCI
352 #endif
353
354 #if defined(CFG_RAMBOOT)
355 #undef CONFIG_CMD_SAVEENV
356 #undef CONFIG_CMD_LOADS
357 #endif
358
359 /*
360  * For booting Linux, the board info and command line data
361  * have to be in the first 256 MB of memory, since this is
362  * the maximum mapped by the Linux kernel during initialization.
363  */
364 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20) /* Initial Memory map for Linux */
365
366 /*
367  * Core HID Setup
368  */
369 #define CONFIG_SYS_HID0_INIT            0x000000000
370 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
371                                          HID0_ENABLE_INSTRUCTION_CACHE)
372 #define CONFIG_SYS_HID2                 HID2_HBE
373
374 /*
375  * MMU Setup
376  */
377
378 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
379
380 /* DDR: cache cacheable */
381 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
382                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
383 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
384 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
385 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
386
387 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
388 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
389                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
390 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
391 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
392 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
393
394 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
395 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
396 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
397 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
398                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
399 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
400
401 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
402 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
403 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
404 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
405                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
406 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
407
408 /* Stack in dcache: cacheable, no memory coherence */
409 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
410 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
411 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
412 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
413
414 /* PAXE:  icache cacheable, but dcache-inhibit and guarded */
415 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
416 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
417 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
418                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
419 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
420
421 #ifdef CONFIG_PCI
422 /* PCI MEM space: cacheable */
423 #define CFG_IBAT6L      (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
424 #define CFG_IBAT6U      (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
425 #define CFG_DBAT6L      CFG_IBAT6L
426 #define CFG_DBAT6U      CFG_IBAT6U
427 /* PCI MMIO space: cache-inhibit and guarded */
428 #define CFG_IBAT7L      (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
429                          BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
430 #define CFG_IBAT7U      (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
431 #define CFG_DBAT7L      CFG_IBAT7L
432 #define CFG_DBAT7U      CFG_IBAT7U
433 #else /* CONFIG_PCI */
434 #define CONFIG_SYS_IBAT6L       (0)
435 #define CONFIG_SYS_IBAT6U       (0)
436 #define CONFIG_SYS_IBAT7L       (0)
437 #define CONFIG_SYS_IBAT7U       (0)
438 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
439 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
440 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
441 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
442 #endif /* CONFIG_PCI */
443
444 #define BOOTFLASH_START F0000000
445
446 #define CONFIG_PRAM     512     /* protected RAM [KBytes] */
447
448 /*
449  * Environment Configuration
450  */
451 #define CONFIG_ENV_OVERWRITE
452 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
453 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
454 #endif
455
456 #define CONFIG_EXTRA_ENV_SETTINGS \
457        CONFIG_KM_DEF_ENV                                                \
458         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
459         "addcon=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
460         "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0"                     \
461         "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0"              \
462         "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0"                      \
463         "loadkernel=tftp ${kernel_addr_r} ${bootfile}\0"                \
464         "unlock=yes\0"                                                  \
465         "fdt_addr=F0080000\0"                                           \
466         "kernel_addr=F00a0000\0"                                        \
467         "ramdisk_addr=F03a0000\0"                                       \
468         "ramdisk_addr_r=F10000\0"                                       \
469         "EEprom_ivm=pca9547:70:9\0"                                     \
470         "dtt_bus=pca9547:70:a\0"                                        \
471         "mtdids=nor0=app \0"                                            \
472         "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0"                       \
473    ""
474
475 #if defined(CONFIG_UEC_ETH)
476 #define CONFIG_HAS_ETH0
477 #endif
478
479 #endif /* __CONFIG_H */