1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
5 * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
11 /* KMBEC FPGA (PRIO) */
12 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
13 #define CONFIG_SYS_KMBEC_FPGA_SIZE 64
15 #define CONFIG_HOSTNAME "kmeter1"
16 #define CONFIG_KM_BOARD_NAME "kmeter1"
17 #define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
20 * High Level Configuration Options
22 #define CONFIG_QE /* Has QE */
24 /* include common defines/options for all Keymile boards */
25 #include "km/keymile-common.h"
26 #include "km/km-powerpc.h"
31 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
32 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
34 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
35 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
36 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
38 #define CFG_83XX_DDR_USES_CS0
41 * Manually set up DDR parameters
44 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */
49 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
50 #define CONFIG_SYS_FLASH_BASE 0xF0000000
52 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
53 #define CONFIG_SYS_RAMBOOT
56 /* Reserve 768 kB for Mon */
57 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
60 * Initial RAM Base Address Setup
62 #define CONFIG_SYS_INIT_RAM_LOCK
63 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
64 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
65 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
66 GENERATED_GBL_DATA_SIZE)
69 * Init Local Bus Memory Controller:
71 * Bank Bus Machine PortSz Size Device
72 * ---- --- ------- ------ ----- ------
73 * 0 Local GPCM 16 bit 256MB FLASH
74 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
78 * FLASH on the Local Bus
80 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
83 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
84 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
85 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
88 * PRIO1/PIGGY on the local bus CS1
95 #define CONFIG_CONS_INDEX 1
96 #define CONFIG_SYS_NS16550_SERIAL
97 #define CONFIG_SYS_NS16550_REG_SIZE 1
98 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
100 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
101 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
104 * QE UEC ethernet configuration
106 #define CONFIG_UEC_ETH
107 #define CONFIG_ETHPRIME "UEC0"
109 #define CONFIG_UEC_ETH1 /* GETH1 */
110 #define UEC_VERBOSE_DEBUG 1
112 #ifdef CONFIG_UEC_ETH1
113 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
114 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
115 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
116 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
117 #define CONFIG_SYS_UEC1_PHY_ADDR 0
118 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
119 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
126 #ifndef CONFIG_SYS_RAMBOOT
127 #ifndef CONFIG_ENV_ADDR
128 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
129 CONFIG_SYS_MONITOR_LEN)
131 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
132 #ifndef CONFIG_ENV_OFFSET
133 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
136 /* Address and size of Redundant Environment Sector */
137 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
138 CONFIG_ENV_SECT_SIZE)
139 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
141 #else /* CFG_SYS_RAMBOOT */
142 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
143 #define CONFIG_ENV_SIZE 0x2000
144 #endif /* CFG_SYS_RAMBOOT */
147 #define CONFIG_SYS_I2C
148 #define CONFIG_SYS_NUM_I2C_BUSES 4
149 #define CONFIG_SYS_I2C_MAX_HOPS 1
150 #define CONFIG_SYS_I2C_FSL
151 #define CONFIG_SYS_FSL_I2C_SPEED 200000
152 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
153 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
154 #define CONFIG_SYS_I2C_OFFSET 0x3000
155 #define CONFIG_SYS_FSL_I2C2_SPEED 200000
156 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
157 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
158 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
159 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
160 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
161 {1, {I2C_NULL_HOP} } }
163 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
165 #if defined(CONFIG_CMD_NAND)
166 #define CONFIG_NAND_KMETER1
167 #define CONFIG_SYS_MAX_NAND_DEVICE 1
168 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
172 * For booting Linux, the board info and command line data
173 * have to be in the first 8 MB of memory, since this is
174 * the maximum mapped by the Linux kernel during initialization.
176 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
179 * Internal Definitions
181 #define BOOTFLASH_START 0xF0000000
183 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
186 * Environment Configuration
188 #define CONFIG_ENV_OVERWRITE
189 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
190 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
193 #ifndef CONFIG_KM_DEF_ARCH
194 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
197 #define CONFIG_EXTRA_ENV_SETTINGS \
201 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \
202 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \
206 #if defined(CONFIG_UEC_ETH)
207 #define CONFIG_HAS_ETH0
213 #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
218 #define CONFIG_SYS_DDR_SDRAM_CFG (\
219 SDRAM_CFG_SDRAM_TYPE_DDR2 | \
223 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
225 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
226 CSCONFIG_ROW_BIT_13 | \
227 CSCONFIG_COL_BIT_10 | \
228 CSCONFIG_ODT_WR_ONLY_CURRENT)
230 #define CONFIG_SYS_DDR_CLK_CNTL (\
231 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
233 #define CONFIG_SYS_DDR_INTERVAL (\
234 (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
235 (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
237 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
239 #define CONFIG_SYS_DDRCDR (\
242 #define CONFIG_SYS_DDR_MODE 0x47860452
243 #define CONFIG_SYS_DDR_MODE2 0x8080c000
245 #define CONFIG_SYS_DDR_TIMING_0 (\
246 (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
247 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
248 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
249 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
250 (0 << TIMING_CFG0_WWT_SHIFT) | \
251 (0 << TIMING_CFG0_RRT_SHIFT) | \
252 (0 << TIMING_CFG0_WRT_SHIFT) | \
253 (0 << TIMING_CFG0_RWT_SHIFT))
255 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
256 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
257 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
258 (3 << TIMING_CFG1_WRREC_SHIFT) | \
259 (7 << TIMING_CFG1_REFREC_SHIFT) | \
260 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
261 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
262 (3 << TIMING_CFG1_PRETOACT_SHIFT))
264 #define CONFIG_SYS_DDR_TIMING_2 (\
265 (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
266 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
267 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
268 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
269 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
270 (5 << TIMING_CFG2_CPO_SHIFT) | \
271 (0 << TIMING_CFG2_ADD_LAT_SHIFT))
273 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
276 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
279 * PAXE on the local bus CS3
281 #define CONFIG_SYS_PAXE_BASE 0xA0000000
282 #define CONFIG_SYS_PAXE_SIZE 256