1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
5 * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
11 /* KMBEC FPGA (PRIO) */
12 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
13 #define CONFIG_SYS_KMBEC_FPGA_SIZE 64
15 #define CONFIG_HOSTNAME "kmeter1"
16 #define CONFIG_KM_BOARD_NAME "kmeter1"
17 #define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
20 * High Level Configuration Options
22 #define CONFIG_QE /* Has QE */
24 /* include common defines/options for all Keymile boards */
25 #include "km/keymile-common.h"
26 #include "km/km-powerpc.h"
31 #define CONFIG_SYS_IMMR 0xE0000000
34 * Bus Arbitration Configuration Register (ACR)
36 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
37 #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
38 #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
39 #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
44 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
45 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
46 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
48 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
49 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
50 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
52 #define CFG_83XX_DDR_USES_CS0
55 * Manually set up DDR parameters
58 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */
63 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
64 #define CONFIG_SYS_FLASH_BASE 0xF0000000
66 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
67 #define CONFIG_SYS_RAMBOOT
70 /* Reserve 768 kB for Mon */
71 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
74 * Initial RAM Base Address Setup
76 #define CONFIG_SYS_INIT_RAM_LOCK
77 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
78 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
79 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
80 GENERATED_GBL_DATA_SIZE)
83 * Init Local Bus Memory Controller:
85 * Bank Bus Machine PortSz Size Device
86 * ---- --- ------- ------ ----- ------
87 * 0 Local GPCM 16 bit 256MB FLASH
88 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
92 * FLASH on the Local Bus
94 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
96 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
97 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
99 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
100 BR_PS_16 | /* 16 bit port size */ \
101 BR_MS_GPCM | /* MSEL = GPCM */ \
104 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
105 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
107 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
109 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
110 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
111 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
114 * PRIO1/PIGGY on the local bus CS1
116 /* Window base at flash base */
117 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE
118 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
120 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \
121 BR_PS_8 | /* 8 bit port size */ \
122 BR_MS_GPCM | /* MSEL = GPCM */ \
124 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
125 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
127 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
132 #define CONFIG_CONS_INDEX 1
133 #define CONFIG_SYS_NS16550_SERIAL
134 #define CONFIG_SYS_NS16550_REG_SIZE 1
135 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
137 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
138 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
141 * QE UEC ethernet configuration
143 #define CONFIG_UEC_ETH
144 #define CONFIG_ETHPRIME "UEC0"
146 #define CONFIG_UEC_ETH1 /* GETH1 */
147 #define UEC_VERBOSE_DEBUG 1
149 #ifdef CONFIG_UEC_ETH1
150 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
151 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
152 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
153 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
154 #define CONFIG_SYS_UEC1_PHY_ADDR 0
155 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
156 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
163 #ifndef CONFIG_SYS_RAMBOOT
164 #ifndef CONFIG_ENV_ADDR
165 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
166 CONFIG_SYS_MONITOR_LEN)
168 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
169 #ifndef CONFIG_ENV_OFFSET
170 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
173 /* Address and size of Redundant Environment Sector */
174 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
175 CONFIG_ENV_SECT_SIZE)
176 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
178 #else /* CFG_SYS_RAMBOOT */
179 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
180 #define CONFIG_ENV_SIZE 0x2000
181 #endif /* CFG_SYS_RAMBOOT */
184 #define CONFIG_SYS_I2C
185 #define CONFIG_SYS_NUM_I2C_BUSES 4
186 #define CONFIG_SYS_I2C_MAX_HOPS 1
187 #define CONFIG_SYS_I2C_FSL
188 #define CONFIG_SYS_FSL_I2C_SPEED 200000
189 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
190 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
191 #define CONFIG_SYS_I2C_OFFSET 0x3000
192 #define CONFIG_SYS_FSL_I2C2_SPEED 200000
193 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
194 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
195 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
196 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
197 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
198 {1, {I2C_NULL_HOP} } }
200 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
202 #if defined(CONFIG_CMD_NAND)
203 #define CONFIG_NAND_KMETER1
204 #define CONFIG_SYS_MAX_NAND_DEVICE 1
205 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
209 * For booting Linux, the board info and command line data
210 * have to be in the first 8 MB of memory, since this is
211 * the maximum mapped by the Linux kernel during initialization.
213 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
218 #define CONFIG_SYS_HID0_INIT 0x000000000
219 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
220 HID0_ENABLE_INSTRUCTION_CACHE)
221 #define CONFIG_SYS_HID2 HID2_HBE
227 /* DDR: cache cacheable */
228 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
229 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
230 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
232 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
233 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
235 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
236 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
237 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
238 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
240 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
241 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
243 /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
244 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
246 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
248 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
249 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
250 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
252 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
253 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
255 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
257 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
258 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
259 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
261 /* Stack in dcache: cacheable, no memory coherence */
262 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
263 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
265 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
266 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
269 * Internal Definitions
271 #define BOOTFLASH_START 0xF0000000
273 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
276 * Environment Configuration
278 #define CONFIG_ENV_OVERWRITE
279 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
280 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
283 #ifndef CONFIG_KM_DEF_ARCH
284 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
287 #define CONFIG_EXTRA_ENV_SETTINGS \
291 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \
292 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \
296 #if defined(CONFIG_UEC_ETH)
297 #define CONFIG_HAS_ETH0
303 #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
308 #define CONFIG_SYS_DDR_SDRAM_CFG (\
309 SDRAM_CFG_SDRAM_TYPE_DDR2 | \
313 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
315 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
316 CSCONFIG_ROW_BIT_13 | \
317 CSCONFIG_COL_BIT_10 | \
318 CSCONFIG_ODT_WR_ONLY_CURRENT)
320 #define CONFIG_SYS_DDR_CLK_CNTL (\
321 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
323 #define CONFIG_SYS_DDR_INTERVAL (\
324 (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
325 (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
327 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
329 #define CONFIG_SYS_DDRCDR (\
332 #define CONFIG_SYS_DDR_MODE 0x47860452
333 #define CONFIG_SYS_DDR_MODE2 0x8080c000
335 #define CONFIG_SYS_DDR_TIMING_0 (\
336 (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
337 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
338 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
339 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
340 (0 << TIMING_CFG0_WWT_SHIFT) | \
341 (0 << TIMING_CFG0_RRT_SHIFT) | \
342 (0 << TIMING_CFG0_WRT_SHIFT) | \
343 (0 << TIMING_CFG0_RWT_SHIFT))
345 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
346 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
347 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
348 (3 << TIMING_CFG1_WRREC_SHIFT) | \
349 (7 << TIMING_CFG1_REFREC_SHIFT) | \
350 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
351 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
352 (3 << TIMING_CFG1_PRETOACT_SHIFT))
354 #define CONFIG_SYS_DDR_TIMING_2 (\
355 (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
356 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
357 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
358 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
359 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
360 (5 << TIMING_CFG2_CPO_SHIFT) | \
361 (0 << TIMING_CFG2_ADD_LAT_SHIFT))
363 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
366 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
369 * Local Bus Configuration & Clock Setup
371 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
372 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
373 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
376 * PAXE on the local bus CS3
378 #define CONFIG_SYS_PAXE_BASE 0xA0000000
379 #define CONFIG_SYS_PAXE_SIZE 256
381 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
383 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
385 #define CONFIG_SYS_BR3_PRELIM (\
386 CONFIG_SYS_PAXE_BASE | \
387 (1 << BR_PS_SHIFT) | \
390 #define CONFIG_SYS_OR3_PRELIM (\
391 MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
402 /* PAXE: icache cacheable, but dcache-inhibit and guarded */
403 #define CONFIG_SYS_IBAT5L (\
404 CONFIG_SYS_PAXE_BASE | \
408 #define CONFIG_SYS_IBAT5U (\
409 CONFIG_SYS_PAXE_BASE | \
414 #define CONFIG_SYS_DBAT5L (\
415 CONFIG_SYS_PAXE_BASE | \
417 BATL_CACHEINHIBIT | \
420 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
421 #define CONFIG_SYS_IBAT6L (0)
422 #define CONFIG_SYS_IBAT6U (0)
423 #define CONFIG_SYS_IBAT7L (0)
424 #define CONFIG_SYS_IBAT7U (0)
425 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
426 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
427 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
428 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U