include/configs/kmeter1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2012
   4  * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
   5  * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /* KMBEC FPGA (PRIO) */
  12 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
  13 #define CONFIG_SYS_KMBEC_FPGA_SIZE      64
  14
  15 #define CONFIG_HOSTNAME         "kmeter1"
  16 #define CONFIG_KM_BOARD_NAME   "kmeter1"
  17 #define CONFIG_KM_DEF_NETDEV    "netdev=eth2\0"
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22 #define CONFIG_QE                       /* Has QE */
  23
  24 /* include common defines/options for all Keymile boards */
  25 #include "km/keymile-common.h"
  26 #include "km/km-powerpc.h"
  27
  28 /*
  29  * IMMR new address
  30  */
  31 #define CONFIG_SYS_IMMR         0xE0000000
  32
  33 /*
  34  * Bus Arbitration Configuration Register (ACR)
  35  */
  36 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  37 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  38 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  39 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  40
  41 /*
  42  * DDR Setup
  43  */
  44 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  45 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  46 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  47
  48 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  49 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  50                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  51
  52 #define CFG_83XX_DDR_USES_CS0
  53
  54 /*
  55  * Manually set up DDR parameters
  56  */
  57 #define CONFIG_DDR_II
  58 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  59
  60 /*
  61  * The reserved memory
  62  */
  63 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  64 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  65
  66 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  67 #define CONFIG_SYS_RAMBOOT
  68 #endif
  69
  70 /* Reserve 768 kB for Mon */
  71 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  72
  73 /*
  74  * Initial RAM Base Address Setup
  75  */
  76 #define CONFIG_SYS_INIT_RAM_LOCK
  77 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  78 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  79 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  80                                                 GENERATED_GBL_DATA_SIZE)
  81
  82 /*
  83  * Init Local Bus Memory Controller:
  84  *
  85  * Bank Bus     Machine PortSz  Size  Device
  86  * ---- ---     ------- ------  -----  ------
  87  *  0   Local   GPCM    16 bit  256MB FLASH
  88  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
  89  *
  90  */
  91 /*
  92  * FLASH on the Local Bus
  93  */
  94 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
  95
  96 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
  97 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
  98
  99 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 100                                 BR_PS_16 | /* 16 bit port size */ \
 101                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 102                                 BR_V)
 103
 104 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 105                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 106                                 OR_GPCM_SCY_5 | \
 107                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 108
 109 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 110 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 111 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 112
 113 /*
 114  * PRIO1/PIGGY on the local bus CS1
 115  */
 116 /* Window base at flash base */
 117 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_KMBEC_FPGA_BASE
 118 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128MB)
 119
 120 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_KMBEC_FPGA_BASE | \
 121                                 BR_PS_8 | /* 8 bit port size */ \
 122                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 123                                 BR_V)
 124 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
 125                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 126                                 OR_GPCM_SCY_2 | \
 127                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 128
 129 /*
 130  * Serial Port
 131  */
 132 #define CONFIG_CONS_INDEX       1
 133 #define CONFIG_SYS_NS16550_SERIAL
 134 #define CONFIG_SYS_NS16550_REG_SIZE     1
 135 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 136
 137 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 138 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 139
 140 /*
 141  * QE UEC ethernet configuration
 142  */
 143 #define CONFIG_UEC_ETH
 144 #define CONFIG_ETHPRIME         "UEC0"
 145
 146 #define CONFIG_UEC_ETH1         /* GETH1 */
 147 #define UEC_VERBOSE_DEBUG       1
 148
 149 #ifdef CONFIG_UEC_ETH1
 150 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 151 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 152 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 153 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 154 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 155 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 156 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 157 #endif
 158
 159 /*
 160  * Environment
 161  */
 162
 163 #ifndef CONFIG_SYS_RAMBOOT
 164 #ifndef CONFIG_ENV_ADDR
 165 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 166                                         CONFIG_SYS_MONITOR_LEN)
 167 #endif
 168 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 169 #ifndef CONFIG_ENV_OFFSET
 170 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 171 #endif
 172
 173 /* Address and size of Redundant Environment Sector     */
 174 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 175                                                 CONFIG_ENV_SECT_SIZE)
 176 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 177
 178 #else /* CFG_SYS_RAMBOOT */
 179 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 180 #define CONFIG_ENV_SIZE         0x2000
 181 #endif /* CFG_SYS_RAMBOOT */
 182
 183 /* I2C */
 184 #define CONFIG_SYS_I2C
 185 #define CONFIG_SYS_NUM_I2C_BUSES        4
 186 #define CONFIG_SYS_I2C_MAX_HOPS         1
 187 #define CONFIG_SYS_I2C_FSL
 188 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 189 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 190 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 191 #define CONFIG_SYS_I2C_OFFSET           0x3000
 192 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 193 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 194 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 195 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 196                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 197                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 198                 {1, {I2C_NULL_HOP} } }
 199
 200 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 201
 202 #if defined(CONFIG_CMD_NAND)
 203 #define CONFIG_NAND_KMETER1
 204 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 205 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 206 #endif
 207
 208 /*
 209  * For booting Linux, the board info and command line data
 210  * have to be in the first 8 MB of memory, since this is
 211  * the maximum mapped by the Linux kernel during initialization.
 212  */
 213 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 214
 215 /*
 216  * Core HID Setup
 217  */
 218 #define CONFIG_SYS_HID0_INIT            0x000000000
 219 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 220                                          HID0_ENABLE_INSTRUCTION_CACHE)
 221 #define CONFIG_SYS_HID2                 HID2_HBE
 222
 223 /*
 224  * MMU Setup
 225  */
 226
 227 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 228
 229 /* DDR: cache cacheable */
 230 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 231                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 232 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 233                                         BATU_VS | BATU_VP)
 234 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 235 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 236
 237 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 238 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 239                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 240 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
 241                                         | BATU_VP)
 242 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 243 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 244
 245 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 246 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 247                                 BATL_MEMCOHERENCE)
 248 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
 249                                 BATU_VS | BATU_VP)
 250 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 251                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 252 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 253
 254 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 255 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 256                                         BATL_MEMCOHERENCE)
 257 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
 258                                         BATU_VS | BATU_VP)
 259 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 260                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 261 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 262
 263 /* Stack in dcache: cacheable, no memory coherence */
 264 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 265 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 266                                         BATU_VS | BATU_VP)
 267 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 268 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 269
 270 /*
 271  * Internal Definitions
 272  */
 273 #define BOOTFLASH_START 0xF0000000
 274
 275 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 276
 277 /*
 278  * Environment Configuration
 279  */
 280 #define CONFIG_ENV_OVERWRITE
 281 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 282 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 283 #endif
 284
 285 #ifndef CONFIG_KM_DEF_ARCH
 286 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 287 #endif
 288
 289 #define CONFIG_EXTRA_ENV_SETTINGS \
 290         CONFIG_KM_DEF_ENV                                               \
 291         CONFIG_KM_DEF_ARCH                                              \
 292         "newenv="                                                       \
 293                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 294                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 295         "unlock=yes\0"                                                  \
 296         ""
 297
 298 #if defined(CONFIG_UEC_ETH)
 299 #define CONFIG_HAS_ETH0
 300 #endif
 301
 302 /*
 303  * System IO Setup
 304  */
 305 #define CONFIG_SYS_SICRH                (SICRH_UC1EOBI | SICRH_UC2E1OBI)
 306
 307 /*
 308  * Hardware Reset Configuration Word
 309  */
 310 #define CONFIG_SYS_HRCW_LOW (\
 311         HRCWL_CSB_TO_CLKIN_4X1 | \
 312         HRCWL_CORE_TO_CSB_2X1 | \
 313         HRCWL_CE_PLL_VCO_DIV_2 | \
 314         HRCWL_CE_TO_PLL_1X6)
 315
 316 #define CONFIG_SYS_HRCW_HIGH (\
 317         HRCWH_CORE_ENABLE | \
 318         HRCWH_FROM_0X00000100 | \
 319         HRCWH_BOOTSEQ_DISABLE | \
 320         HRCWH_SW_WATCHDOG_DISABLE | \
 321         HRCWH_ROM_LOC_LOCAL_16BIT | \
 322         HRCWH_BIG_ENDIAN | \
 323         HRCWH_LALE_EARLY | \
 324         HRCWH_LDP_CLEAR)
 325
 326 /**
 327  * DDR RAM settings
 328  */
 329 #define CONFIG_SYS_DDR_SDRAM_CFG (\
 330         SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 331         SDRAM_CFG_SREN | \
 332         SDRAM_CFG_HSE)
 333
 334 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 335
 336 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 337                                          CSCONFIG_ROW_BIT_13 | \
 338                                          CSCONFIG_COL_BIT_10 | \
 339                                          CSCONFIG_ODT_WR_ONLY_CURRENT)
 340
 341 #define CONFIG_SYS_DDR_CLK_CNTL (\
 342         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 343
 344 #define CONFIG_SYS_DDR_INTERVAL (\
 345         (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 346         (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
 347
 348 #define CONFIG_SYS_DDR_CS0_BNDS                 0x0000007f
 349
 350 #define CONFIG_SYS_DDRCDR (\
 351         DDRCDR_EN | \
 352         DDRCDR_Q_DRN)
 353 #define CONFIG_SYS_DDR_MODE             0x47860452
 354 #define CONFIG_SYS_DDR_MODE2            0x8080c000
 355
 356 #define CONFIG_SYS_DDR_TIMING_0 (\
 357         (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 358         (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 359         (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 360         (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 361         (0 << TIMING_CFG0_WWT_SHIFT) | \
 362         (0 << TIMING_CFG0_RRT_SHIFT) | \
 363         (0 << TIMING_CFG0_WRT_SHIFT) | \
 364         (0 << TIMING_CFG0_RWT_SHIFT))
 365
 366 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
 367                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 368                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 369                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 370                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 371                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 372                                  (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 373                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 374
 375 #define CONFIG_SYS_DDR_TIMING_2 (\
 376         (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 377         (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 378         (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 379         (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 380         (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 381         (5 << TIMING_CFG2_CPO_SHIFT) | \
 382         (0 << TIMING_CFG2_ADD_LAT_SHIFT))
 383
 384 #define CONFIG_SYS_DDR_TIMING_3                 0x00000000
 385
 386 /* EEprom support */
 387 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 388
 389 /*
 390  * Local Bus Configuration & Clock Setup
 391  */
 392 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 393 #define CONFIG_SYS_LCRR_EADC            LCRR_EADC_2
 394 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_4
 395
 396 /*
 397  * PAXE on the local bus CS3
 398  */
 399 #define CONFIG_SYS_PAXE_BASE            0xA0000000
 400 #define CONFIG_SYS_PAXE_SIZE            256
 401
 402 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PAXE_BASE
 403
 404 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000001C /* 512MB window size */
 405
 406 #define CONFIG_SYS_BR3_PRELIM (\
 407         CONFIG_SYS_PAXE_BASE | \
 408         (1 << BR_PS_SHIFT) | \
 409         BR_V)
 410
 411 #define CONFIG_SYS_OR3_PRELIM (\
 412         MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
 413         OR_GPCM_CSNT | \
 414         OR_GPCM_ACS_DIV2 | \
 415         OR_GPCM_SCY_2 | \
 416         OR_GPCM_TRLX | \
 417         OR_GPCM_EAD)
 418
 419 /*
 420  * MMU Setup
 421  */
 422
 423 /* PAXE:  icache cacheable, but dcache-inhibit and guarded */
 424 #define CONFIG_SYS_IBAT5L (\
 425         CONFIG_SYS_PAXE_BASE | \
 426         BATL_PP_10 | \
 427         BATL_MEMCOHERENCE)
 428
 429 #define CONFIG_SYS_IBAT5U (\
 430         CONFIG_SYS_PAXE_BASE | \
 431         BATU_BL_256M | \
 432         BATU_VS | \
 433         BATU_VP)
 434
 435 #define CONFIG_SYS_DBAT5L (\
 436         CONFIG_SYS_PAXE_BASE | \
 437         BATL_PP_10 | \
 438         BATL_CACHEINHIBIT | \
 439         BATL_GUARDEDSTORAGE)
 440
 441 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 442 #define CONFIG_SYS_IBAT6L       (0)
 443 #define CONFIG_SYS_IBAT6U       (0)
 444 #define CONFIG_SYS_IBAT7L       (0)
 445 #define CONFIG_SYS_IBAT7U       (0)
 446 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 447 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 448 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 449 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 450
 451 #endif /* CONFIG */