1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
5 * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
11 /* KMBEC FPGA (PRIO) */
12 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
13 #define CONFIG_SYS_KMBEC_FPGA_SIZE 64
15 #define CONFIG_HOSTNAME "kmcoge5ne"
16 #define CONFIG_KM_BOARD_NAME "kmcoge5ne"
17 #define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
18 #define CONFIG_NAND_ECC_BCH
19 #define CONFIG_NAND_KMETER1
20 #define CONFIG_SYS_MAX_NAND_DEVICE 1
21 #define NAND_MAX_CHIPS 1
22 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
24 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
25 #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
28 * High Level Configuration Options
30 #define CONFIG_QE /* Has QE */
32 /* include common defines/options for all Keymile boards */
33 #include "km/keymile-common.h"
34 #include "km/km-powerpc.h"
39 #define CONFIG_83XX_CLKIN 66000000
40 #define CONFIG_SYS_CLK_FREQ 66000000
41 #define CONFIG_83XX_PCICLK 66000000
46 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
47 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
49 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
50 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
51 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
53 #define CFG_83XX_DDR_USES_CS0
56 * Manually set up DDR parameters
59 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */
64 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
65 #define CONFIG_SYS_FLASH_BASE 0xF0000000
67 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
68 #define CONFIG_SYS_RAMBOOT
71 /* Reserve 768 kB for Mon */
72 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
75 * Initial RAM Base Address Setup
77 #define CONFIG_SYS_INIT_RAM_LOCK
78 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
79 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
80 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
81 GENERATED_GBL_DATA_SIZE)
84 * Init Local Bus Memory Controller:
86 * Bank Bus Machine PortSz Size Device
87 * ---- --- ------- ------ ----- ------
88 * 0 Local GPCM 16 bit 256MB FLASH
89 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
93 * FLASH on the Local Bus
95 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
98 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
99 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
100 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
103 * PRIO1/PIGGY on the local bus CS1
110 #define CONFIG_SYS_NS16550_SERIAL
111 #define CONFIG_SYS_NS16550_REG_SIZE 1
112 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
114 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
115 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
118 * QE UEC ethernet configuration
120 #define CONFIG_UEC_ETH
121 #define CONFIG_ETHPRIME "UEC0"
123 #define CONFIG_UEC_ETH1 /* GETH1 */
124 #define UEC_VERBOSE_DEBUG 1
126 #ifdef CONFIG_UEC_ETH1
127 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
128 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
129 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
130 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
131 #define CONFIG_SYS_UEC1_PHY_ADDR 0
132 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
133 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
140 #ifndef CONFIG_SYS_RAMBOOT
141 #ifndef CONFIG_ENV_ADDR
142 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
143 CONFIG_SYS_MONITOR_LEN)
145 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
146 #ifndef CONFIG_ENV_OFFSET
147 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
150 /* Address and size of Redundant Environment Sector */
151 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
152 CONFIG_ENV_SECT_SIZE)
153 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
155 #else /* CFG_SYS_RAMBOOT */
156 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
157 #define CONFIG_ENV_SIZE 0x2000
158 #endif /* CFG_SYS_RAMBOOT */
161 #define CONFIG_SYS_I2C
162 #define CONFIG_SYS_NUM_I2C_BUSES 4
163 #define CONFIG_SYS_I2C_MAX_HOPS 1
164 #define CONFIG_SYS_I2C_FSL
165 #define CONFIG_SYS_FSL_I2C_SPEED 200000
166 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
167 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
168 #define CONFIG_SYS_I2C_OFFSET 0x3000
169 #define CONFIG_SYS_FSL_I2C2_SPEED 200000
170 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
171 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
172 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
173 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
174 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
175 {1, {I2C_NULL_HOP} } }
177 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
179 #if defined(CONFIG_CMD_NAND)
180 #define CONFIG_NAND_KMETER1
181 #define CONFIG_SYS_MAX_NAND_DEVICE 1
182 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
186 * For booting Linux, the board info and command line data
187 * have to be in the first 8 MB of memory, since this is
188 * the maximum mapped by the Linux kernel during initialization.
190 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
193 * Internal Definitions
195 #define BOOTFLASH_START 0xF0000000
197 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
200 * Environment Configuration
202 #define CONFIG_ENV_OVERWRITE
203 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
204 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
207 #ifndef CONFIG_KM_DEF_ARCH
208 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
211 #define CONFIG_EXTRA_ENV_SETTINGS \
215 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \
216 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \
220 #if defined(CONFIG_UEC_ETH)
221 #define CONFIG_HAS_ETH0
227 #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
232 #define CONFIG_SYS_DDR_SDRAM_CFG (\
233 SDRAM_CFG_SDRAM_TYPE_DDR2 | \
237 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
240 * KMCOGE5NE has 512 MB RAM
242 #define CONFIG_SYS_DDR_CS0_CONFIG (\
245 CSCONFIG_ODT_WR_ONLY_CURRENT | \
246 CSCONFIG_BANK_BIT_3 | \
247 CSCONFIG_ROW_BIT_13 | \
250 #define CONFIG_SYS_DDR_CLK_CNTL (\
251 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
253 #define CONFIG_SYS_DDR_INTERVAL (\
254 (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
255 (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
257 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
259 #define CONFIG_SYS_DDRCDR (\
262 #define CONFIG_SYS_DDR_MODE 0x47860452
263 #define CONFIG_SYS_DDR_MODE2 0x8080c000
265 #define CONFIG_SYS_DDR_TIMING_0 (\
266 (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
267 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
268 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
269 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
270 (0 << TIMING_CFG0_WWT_SHIFT) | \
271 (0 << TIMING_CFG0_RRT_SHIFT) | \
272 (0 << TIMING_CFG0_WRT_SHIFT) | \
273 (0 << TIMING_CFG0_RWT_SHIFT))
275 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
276 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
277 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
278 (3 << TIMING_CFG1_WRREC_SHIFT) | \
279 (7 << TIMING_CFG1_REFREC_SHIFT) | \
280 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
281 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
282 (3 << TIMING_CFG1_PRETOACT_SHIFT))
284 #define CONFIG_SYS_DDR_TIMING_2 (\
285 (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
286 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
287 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
288 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
289 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
290 (5 << TIMING_CFG2_CPO_SHIFT) | \
291 (0 << TIMING_CFG2_ADD_LAT_SHIFT))
293 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
296 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
299 * PAXE on the local bus CS3
301 #define CONFIG_SYS_PAXE_BASE 0xA0000000
302 #define CONFIG_SYS_PAXE_SIZE 256
306 * BFTIC3 on the local bus CS4
308 #define CONFIG_SYS_BFTIC3_BASE 0xB0000000
309 #define CONFIG_SYS_BFTIC3_SIZE 256
312 /* enable POST tests */
313 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
314 #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
315 #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
316 #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
317 #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */