include/configs/kmcent2.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2016 Keymile AG
   4  * Rainer Boschung <rainer.boschung@keymile.com>
   5  *
   6  */
   7
   8 #ifndef __KMCENT2_H
   9 #define __KMCENT2_H
  10
  11 #define CONFIG_HOSTNAME         "kmcent2"
  12 #define KM_BOARD_NAME   CONFIG_HOSTNAME
  13
  14 /*
  15  * The Linux fsl_fman driver needs to be able to process frames with more
  16  * than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot
  17  * parameters
  18  */
  19 #define CONFIG_KM_DEF_BOOT_ARGS_CPU     "fsl_dpaa_fman.fsl_fm_max_frm=1558"
  20
  21 #include "km/keymile-common.h"
  22
  23 /* Application IFC chip selects */
  24 #define SYS_LAWAPP_BASE         0xc0000000
  25 #define SYS_LAWAPP_BASE_PHYS    (0xf00000000ull | SYS_LAWAPP_BASE)
  26
  27 /* Application IFC CS4 MRAM */
  28 #define CFG_SYS_MRAM_BASE               SYS_LAWAPP_BASE
  29 #define SYS_MRAM_BASE_PHYS      SYS_LAWAPP_BASE_PHYS
  30 #define SYS_MRAM_CSPR_EXT       (0x0f)
  31 #define SYS_MRAM_CSPR   (CSPR_PHYS_ADDR(CFG_SYS_MRAM_BASE) | \
  32                                 CSPR_PORT_SIZE_8 | /* 8 bit */          \
  33                                 CSPR_MSEL_GPCM   | /* msel = gpcm */    \
  34                                 CSPR_V /* bank is valid */)
  35 #define SYS_MRAM_AMASK          IFC_AMASK(2 * 1024 * 1024) /* 2 MiB */
  36 #define SYS_MRAM_CSOR           CSOR_GPCM_TRHZ_40
  37 /* MRAM Timing parameters for IFC CS4 */
  38 #define SYS_MRAM_FTIM0  (FTIM0_GPCM_TACSE(0x6) | \
  39                         FTIM0_GPCM_TEADC(0x8)  | \
  40                         FTIM0_GPCM_TEAHC(0x2))
  41 #define SYS_MRAM_FTIM1  (FTIM1_GPCM_TACO(0x2) | \
  42                         FTIM1_GPCM_TRAD(0xe))
  43 #define SYS_MRAM_FTIM2  (FTIM2_GPCM_TCS(0x2) | \
  44                         FTIM2_GPCM_TCH(0x2)  | \
  45                         FTIM2_GPCM_TWP(0x8))
  46 #define SYS_MRAM_FTIM3  0x04000000
  47 #define CFG_SYS_CSPR4_EXT       SYS_MRAM_CSPR_EXT
  48 #define CFG_SYS_CSPR4   SYS_MRAM_CSPR
  49 #define CFG_SYS_AMASK4  SYS_MRAM_AMASK
  50 #define CFG_SYS_CSOR4   SYS_MRAM_CSOR
  51 #define CFG_SYS_CS4_FTIM0       SYS_MRAM_FTIM0
  52 #define CFG_SYS_CS4_FTIM1       SYS_MRAM_FTIM1
  53 #define CFG_SYS_CS4_FTIM2       SYS_MRAM_FTIM2
  54 #define CFG_SYS_CS4_FTIM3       SYS_MRAM_FTIM3
  55
  56 /* Application IFC CS6: BFTIC */
  57 #define SYS_BFTIC_BASE          0xd0000000
  58 #define SYS_BFTIC_BASE_PHYS     (0xf00000000ull | SYS_BFTIC_BASE)
  59 #define SYS_BFTIC_CSPR_EXT      (0x0f)
  60 #define SYS_BFTIC_CSPR  (CSPR_PHYS_ADDR(SYS_BFTIC_BASE) | \
  61                                 CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
  62                                 CSPR_MSEL_GPCM |   /* MSEL = GPCM */\
  63                                 CSPR_V)            /* valid */
  64 #define SYS_BFTIC_AMASK IFC_AMASK(64 * 1024)  /* 64kB */
  65 #define SYS_BFTIC_CSOR  CSOR_GPCM_TRHZ_40
  66 /* BFTIC Timing parameters for IFC CS6 */
  67 #define SYS_BFTIC_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
  68                                 FTIM0_GPCM_TEADC(0x8) | \
  69                                 FTIM0_GPCM_TEAHC(0x2))
  70 #define SYS_BFTIC_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
  71                                 FTIM1_GPCM_TRAD(0x12))
  72 #define SYS_BFTIC_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
  73                                 FTIM2_GPCM_TCH(0x1) | \
  74                                 FTIM2_GPCM_TWP(0x12))
  75 #define SYS_BFTIC_FTIM3 0x04000000
  76 #define CFG_SYS_CSPR6_EXT       SYS_BFTIC_CSPR_EXT
  77 #define CFG_SYS_CSPR6   SYS_BFTIC_CSPR
  78 #define CFG_SYS_AMASK6  SYS_BFTIC_AMASK
  79 #define CFG_SYS_CSOR6   SYS_BFTIC_CSOR
  80 #define CFG_SYS_CS6_FTIM0       SYS_BFTIC_FTIM0
  81 #define CFG_SYS_CS6_FTIM1       SYS_BFTIC_FTIM1
  82 #define CFG_SYS_CS6_FTIM2       SYS_BFTIC_FTIM2
  83 #define CFG_SYS_CS6_FTIM3       SYS_BFTIC_FTIM3
  84
  85 /* Application IFC CS7 PAXE */
  86 #define CFG_SYS_PAXE_BASE               0xd8000000
  87 #define SYS_PAXE_BASE_PHYS      (0xf00000000ull | CFG_SYS_PAXE_BASE)
  88 #define SYS_PAXE_CSPR_EXT       (0x0f)
  89 #define SYS_PAXE_CSPR  (CSPR_PHYS_ADDR(CFG_SYS_PAXE_BASE) | \
  90                                 CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
  91                                 CSPR_MSEL_GPCM |   /* MSEL = GPCM */\
  92                                 CSPR_V)            /* valid */
  93 #define SYS_PAXE_AMASK IFC_AMASK(64 * 1024)  /* 64kB */
  94 #define SYS_PAXE_CSOR  CSOR_GPCM_TRHZ_40
  95 /* PAXE Timing parameters for IFC CS7 */
  96 #define SYS_PAXE_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
  97                         FTIM0_GPCM_TEADC(0x8) | \
  98                         FTIM0_GPCM_TEAHC(0x2))
  99 #define SYS_PAXE_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
 100                         FTIM1_GPCM_TRAD(0x12))
 101 #define SYS_PAXE_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
 102                         FTIM2_GPCM_TCH(0x1) | \
 103                         FTIM2_GPCM_TWP(0x12))
 104 #define SYS_PAXE_FTIM3  0x04000000
 105 #define CFG_SYS_CSPR7_EXT       SYS_PAXE_CSPR_EXT
 106 #define CFG_SYS_CSPR7   SYS_PAXE_CSPR
 107 #define CFG_SYS_AMASK7  SYS_PAXE_AMASK
 108 #define CFG_SYS_CSOR7   SYS_PAXE_CSOR
 109 #define CFG_SYS_CS7_FTIM0       SYS_PAXE_FTIM0
 110 #define CFG_SYS_CS7_FTIM1       SYS_PAXE_FTIM1
 111 #define CFG_SYS_CS7_FTIM2       SYS_PAXE_FTIM2
 112 #define CFG_SYS_CS7_FTIM3       SYS_PAXE_FTIM3
 113
 114 /* PRST */
 115 #define KM_BFTIC4_RST           0
 116 #define KM_DPAXE_RST            1
 117 #define KM_FEMT_RST             3
 118 #define KM_FOAM_RST             4
 119 #define KM_EFE_RST              5
 120 #define KM_ES_PHY_RST           6
 121 #define KM_XES_PHY_RST          7
 122 #define KM_ZL30158_RST          8
 123 #define KM_ZL30364_RST          9
 124 #define KM_BOBCAT_RST           10
 125 #define KM_ETHSW_DDR_RST                12
 126 #define KM_CFE_RST              13
 127 #define KM_PEXSW_RST            14
 128 #define KM_PEXSW_NT_RST         15
 129
 130 /* QRIO GPIOs used for deblocking */
 131 #define KM_I2C_DEBLOCK_PORT     QRIO_GPIO_A
 132 #define KM_I2C_DEBLOCK_SCL      20
 133 #define KM_I2C_DEBLOCK_SDA      21
 134
 135 /* High Level Configuration Options */
 136
 137 #define CONFIG_RESET_VECTOR_ADDRESS     0xebfffffc
 138
 139 #define CFG_SYS_NUM_CPC         CONFIG_SYS_NUM_DDR_CTLRS
 140
 141 /* Environment in parallel NOR-Flash */
 142 #define CONFIG_ENV_TOTAL_SIZE           0x040000
 143 #define ENV_DEL_ADDR            0xebf00000      /*direct for newenv*/
 144
 145 /*
 146  * These can be toggled for performance analysis, otherwise use default.
 147  */
 148 #define CFG_SYS_INIT_L2CSR0             L2CSR0_L2E
 149
 150 /* POST memory regions test */
 151 #define CFG_POST CFG_SYS_POST_MEM_REGIONS
 152
 153 /*
 154  *  Config the L3 Cache as L3 SRAM
 155  */
 156 #define CFG_SYS_INIT_L3_ADDR            0xFFFC0000
 157
 158 #define CFG_SYS_DCSRBAR         0xf0000000
 159 #define CFG_SYS_DCSRBAR_PHYS            0xf00000000ull
 160
 161 /*
 162  * DDR Setup
 163  */
 164 #define CONFIG_VERY_BIG_RAM
 165 #define CFG_SYS_DDR_SDRAM_BASE  0x00000000
 166 #define CFG_SYS_SDRAM_BASE              CFG_SYS_DDR_SDRAM_BASE
 167
 168 #define SPD_EEPROM_ADDRESS      0x54
 169 #define CFG_SYS_SDRAM_SIZE      4096    /* for fixed parameter use */
 170
 171 /******************************************************************************
 172  * (PRAM usage)
 173  * ... -------------------------------------------------------
 174  * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
 175  * ... |<------------------- pram -------------------------->|
 176  * ... -------------------------------------------------------
 177  * @END_OF_RAM:
 178  * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
 179  * @CONFIG_KM_PHRAM: address for /var
 180  * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
 181  */
 182
 183 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
 184  * is not valid yet, which is the case for when u-boot copies itself to RAM
 185  */
 186 #define CONFIG_PRAM             ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
 187
 188 /*
 189  * IFC Definitions
 190  */
 191 /* NOR flash on IFC CS0 */
 192 #define CFG_SYS_FLASH_BASE              0xe8000000
 193 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \
 194                                         CFG_SYS_FLASH_BASE)
 195
 196 #define CFG_SYS_NOR_CSPR_EXT    (0x0f)
 197 #define CFG_SYS_NOR_CSPR        (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \
 198                                 CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\
 199                                 0x00000010 |        /* drive TE high */\
 200                                 CSPR_MSEL_NOR |     /* MSEL = NOR */\
 201                                 CSPR_V)             /* valid */
 202 #define CFG_SYS_NOR_AMASK       IFC_AMASK(64 * 1024 * 1024) /* 64MB */
 203 #define CFG_SYS_NOR_CSOR        (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\
 204                                 CSOR_NOR_TRHZ_20 | \
 205                                 CSOR_NOR_BCTLD)
 206
 207 /* NOR Flash Timing Params */
 208 #define CFG_SYS_NOR_FTIM0       (FTIM0_NOR_TACSE(0x1) | \
 209                                 FTIM0_NOR_TEADC(0x7) | \
 210                                 FTIM0_NOR_TEAHC(0x1))
 211 #define CFG_SYS_NOR_FTIM1       (FTIM1_NOR_TACO(0x1) | \
 212                                 FTIM1_NOR_TRAD_NOR(0x21) | \
 213                                 FTIM1_NOR_TSEQRAD_NOR(0x21))
 214 #define CFG_SYS_NOR_FTIM2       (FTIM2_NOR_TCH(0x1) | \
 215                                 FTIM2_NOR_TCS(0x1) | \
 216                                 FTIM2_NOR_TWP(0xb) | \
 217                                 FTIM2_NOR_TWPH(0x6))
 218 #define CFG_SYS_NOR_FTIM3       0x0
 219
 220 #define CFG_SYS_CSPR0_EXT       CFG_SYS_NOR_CSPR_EXT
 221 #define CFG_SYS_CSPR0   CFG_SYS_NOR_CSPR
 222 #define CFG_SYS_AMASK0  CFG_SYS_NOR_AMASK
 223 #define CFG_SYS_CSOR0   CFG_SYS_NOR_CSOR
 224 #define CFG_SYS_CS0_FTIM0       CFG_SYS_NOR_FTIM0
 225 #define CFG_SYS_CS0_FTIM1       CFG_SYS_NOR_FTIM1
 226 #define CFG_SYS_CS0_FTIM2       CFG_SYS_NOR_FTIM2
 227 #define CFG_SYS_CS0_FTIM3       CFG_SYS_NOR_FTIM3
 228
 229 /* More NOR Flash params */
 230
 231 #define CFG_SYS_FLASH_BANKS_LIST        {CFG_SYS_FLASH_BASE_PHYS}
 232
 233 /* NAND Flash on IFC CS1*/
 234 #define CFG_SYS_NAND_BASE               0xfa000000
 235 #define CFG_SYS_NAND_BASE_PHYS  (0xf00000000ull | CFG_SYS_NAND_BASE)
 236
 237 #define CFG_SYS_NAND_CSPR_EXT   (0x0f)
 238 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \
 239                                 CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\
 240                                 0x00000010 |       /* drive TE high */\
 241                                 CSPR_MSEL_NAND |   /* MSEL = NAND */\
 242                                 CSPR_V)            /* valid */
 243 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64 * 1024) /* 64kB */
 244
 245 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
 246                                 CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */   \
 247                                 CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */        \
 248                                 CSOR_NAND_RAL_3      | /* RAL = 3Bytes */     \
 249                                 CSOR_NAND_PGS_2K     | /* Page size = 2K */   \
 250                                 CSOR_NAND_SPRZ_128   | /* Spare size = 128 */ \
 251                                 CSOR_NAND_PB(64)     | /* 64 Pages/Block */   \
 252                                 CSOR_NAND_TRHZ_40    | /**/                   \
 253                                 CSOR_NAND_BCTLD)       /**/
 254
 255 /* ONFI NAND Flash mode0 Timing Params */
 256 #define CFG_SYS_NAND_FTIM0      (FTIM0_NAND_TCCST(0x3) | \
 257                                 FTIM0_NAND_TWP(0x8) | \
 258                                 FTIM0_NAND_TWCHT(0x3) | \
 259                                 FTIM0_NAND_TWH(0x5))
 260 #define CFG_SYS_NAND_FTIM1      (FTIM1_NAND_TADLE(0x1e) | \
 261                                 FTIM1_NAND_TWBE(0x1e) | \
 262                                 FTIM1_NAND_TRR(0x6) | \
 263                                 FTIM1_NAND_TRP(0x8))
 264 #define CFG_SYS_NAND_FTIM2      (FTIM2_NAND_TRAD(0x9) | \
 265                                 FTIM2_NAND_TREH(0x5) | \
 266                                 FTIM2_NAND_TWHRE(0x3c))
 267 #define CFG_SYS_NAND_FTIM3      (FTIM3_NAND_TWW(0x1e))
 268
 269 #define CFG_SYS_CSPR1_EXT       CFG_SYS_NAND_CSPR_EXT
 270 #define CFG_SYS_CSPR1   CFG_SYS_NAND_CSPR
 271 #define CFG_SYS_AMASK1  CFG_SYS_NAND_AMASK
 272 #define CFG_SYS_CSOR1   CFG_SYS_NAND_CSOR
 273 #define CFG_SYS_CS1_FTIM0       CFG_SYS_NAND_FTIM0
 274 #define CFG_SYS_CS1_FTIM1       CFG_SYS_NAND_FTIM1
 275 #define CFG_SYS_CS1_FTIM2       CFG_SYS_NAND_FTIM2
 276 #define CFG_SYS_CS1_FTIM3       CFG_SYS_NAND_FTIM3
 277
 278 /* More NAND Flash Params */
 279 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 280
 281 /* QRIO on IFC CS2 */
 282 #define CFG_SYS_QRIO_BASE               0xfb000000
 283 #define CFG_SYS_QRIO_BASE_PHYS  (0xf00000000ull | CFG_SYS_QRIO_BASE)
 284 #define SYS_QRIO_CSPR_EXT       (0x0f)
 285 #define SYS_QRIO_CSPR   (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \
 286                                 CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
 287                                 0x00000010 |       /* drive TE high */\
 288                                 CSPR_MSEL_GPCM |   /* MSEL = GPCM */\
 289                                 CSPR_V)           /* valid */
 290 #define SYS_QRIO_AMASK  IFC_AMASK(64 * 1024)  /* 64kB */
 291 #define SYS_QRIO_CSOR   (CSOR_GPCM_TRHZ_20 |\
 292                         CSOR_GPCM_BCTLD)
 293 /* QRIO Timing parameters for IFC CS2 */
 294 #define SYS_QRIO_FTIM0  (FTIM0_GPCM_TACSE(0x2) | \
 295                         FTIM0_GPCM_TEADC(0x8) | \
 296                         FTIM0_GPCM_TEAHC(0x2))
 297 #define SYS_QRIO_FTIM1  (FTIM1_GPCM_TACO(0x2) | \
 298                         FTIM1_GPCM_TRAD(0x6))
 299 #define SYS_QRIO_FTIM2  (FTIM2_GPCM_TCS(0x1) | \
 300                         FTIM2_GPCM_TCH(0x1) | \
 301                         FTIM2_GPCM_TWP(0x7))
 302 #define SYS_QRIO_FTIM3  0x04000000
 303 #define CFG_SYS_CSPR2_EXT       SYS_QRIO_CSPR_EXT
 304 #define CFG_SYS_CSPR2   SYS_QRIO_CSPR
 305 #define CFG_SYS_AMASK2  SYS_QRIO_AMASK
 306 #define CFG_SYS_CSOR2   SYS_QRIO_CSOR
 307 #define CFG_SYS_CS2_FTIM0       SYS_QRIO_FTIM0
 308 #define CFG_SYS_CS2_FTIM1       SYS_QRIO_FTIM1
 309 #define CFG_SYS_CS2_FTIM2       SYS_QRIO_FTIM2
 310 #define CFG_SYS_CS2_FTIM3       SYS_QRIO_FTIM3
 311
 312 /* define to use L1 as initial stack */
 313 #define CFG_SYS_INIT_RAM_ADDR   0xfdd00000      /* Initial L1 address */
 314 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 315 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW  0xfe03c000
 316 /* The assembler doesn't like typecast */
 317 #define CFG_SYS_INIT_RAM_ADDR_PHYS \
 318         ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 319           CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 320 #define CFG_SYS_INIT_RAM_SIZE           0x00004000
 321
 322 #define CFG_SYS_INIT_SP_OFFSET  (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 323
 324 /*
 325  * Serial Port - controlled on board with jumper J8
 326  * open - index 2
 327  * shorted - index 1
 328  * Retain non-DM serial port for debug purposes.
 329  */
 330 #if !defined(CONFIG_DM_SERIAL)
 331 #define CFG_SYS_NS16550_CLK             (get_bus_freq(0) / 2)
 332 #define CFG_SYS_NS16550_COM1    (CFG_SYS_CCSRBAR + 0x11C500)
 333 #endif
 334
 335 #ifndef __ASSEMBLY__
 336 void set_sda(int state);
 337 void set_scl(int state);
 338 int get_sda(void);
 339 int get_scl(void);
 340 #endif
 341
 342 /*
 343  * General PCI
 344  * Memory space is mapped 1-1, but I/O space must start from 0.
 345  */
 346 /* controller 1 */
 347 #define CFG_SYS_PCIE1_MEM_VIRT  0x80000000
 348 #define CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
 349 #define CFG_SYS_PCIE1_IO_VIRT   0xf8000000
 350 #define CFG_SYS_PCIE1_IO_PHYS   0xff8000000ull
 351
 352 #define CFG_SYS_BMAN_NUM_PORTALS        10
 353 #define CFG_SYS_BMAN_MEM_BASE   0xf4000000
 354 #define CFG_SYS_BMAN_MEM_PHYS   0xff4000000ull
 355 #define CFG_SYS_BMAN_MEM_SIZE   0x02000000
 356 #define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
 357 #define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 358 #define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
 359                                         CFG_SYS_BMAN_CENA_SIZE)
 360 #define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 361 #define CFG_SYS_BMAN_SWP_ISDR_REG       0xE08
 362 #define CFG_SYS_QMAN_NUM_PORTALS        10
 363 #define CFG_SYS_QMAN_MEM_BASE   0xf6000000
 364 #define CFG_SYS_QMAN_MEM_PHYS   0xff6000000ull
 365 #define CFG_SYS_QMAN_MEM_SIZE   0x02000000
 366 #define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
 367 #define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 368 #define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
 369                                         CFG_SYS_QMAN_CENA_SIZE)
 370 #define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 371 #define CFG_SYS_QMAN_SWP_ISDR_REG       0xE08
 372
 373 /* Qman / Bman */
 374 /* RGMII (FM1@DTESC5) is local managemant interface */
 375 #define CFG_SYS_RGMII2_PHY_ADDR             0x11
 376
 377 /*
 378  * Hardware Watchdog
 379  */
 380 #define CONFIG_WATCHDOG_PRESC 34        /* wdog prescaler 2^(64-34) ~10min */
 381 #define CONFIG_WATCHDOG_RC WRC_CHIP     /* reset chip on watchdog event */
 382
 383 /*
 384  * For booting Linux, the board info and command line data
 385  * have to be in the first 64 MB of memory, since this is
 386  * the maximum mapped by the Linux kernel during initialization.
 387  */
 388 #define CFG_SYS_BOOTMAPSZ       (64 << 20)      /* Initial map for Linux*/
 389
 390 /*
 391  * Environment Configuration
 392  */
 393 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 394 #define CONFIG_KM_DEF_ENV
 395 #endif
 396
 397 #define __USB_PHY_TYPE  utmi
 398
 399 #define CONFIG_KM_DEF_ENV_CPU                                           \
 400         "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"                   \
 401         "cramfsloadfdt="                                                \
 402                 "cramfsload ${fdt_addr_r} "                             \
 403                 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"             \
 404         "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"               \
 405         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 406                 " +${filesize} && "                                     \
 407                 "erase " __stringify(CONFIG_SYS_MONITOR_BASE)           \
 408                 " +${filesize} && "                                     \
 409                 "cp.b ${load_addr_r} "                                  \
 410                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
 411                 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 412                 " +${filesize}\0"                                       \
 413         "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE)       \
 414                 " +${filesize} && "                                     \
 415                 "erase " __stringify(CFG_SYS_FLASH_BASE)                \
 416                 " +${filesize} && "                                     \
 417                 "cp.b ${load_addr_r} "                                  \
 418                 __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && "      \
 419                 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 420                 " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0"           \
 421         "set_fdthigh=true\0"                                            \
 422         "checkfdt=true\0"                                               \
 423         "fpgacfg=true\0"                                                \
 424         ""
 425
 426 #define CONFIG_HW_ENV_SETTINGS                                          \
 427         "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0"                       \
 428         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 429         "usb_dr_mode=host\0"
 430
 431 #define CONFIG_KM_NEW_ENV                                               \
 432         "newenv=protect off " __stringify(ENV_DEL_ADDR)                 \
 433                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "          \
 434                 "erase " __stringify(ENV_DEL_ADDR)                      \
 435                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "          \
 436                 "protect on " __stringify(ENV_DEL_ADDR)                 \
 437                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
 438
 439 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
 440 #ifndef CONFIG_KM_DEF_ARCH
 441 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 442 #endif
 443
 444 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 445         CONFIG_KM_DEF_ENV                                               \
 446         CONFIG_KM_DEF_ARCH                                              \
 447         CONFIG_KM_NEW_ENV                                               \
 448         CONFIG_HW_ENV_SETTINGS                                          \
 449         "EEprom_ivm=pca9547:70:9\0"                                     \
 450         ""
 451
 452 #endif  /* __KMCENT2_H */