Convert CONFIG_ESDHC_DETECT_QUIRK to Kconfig
[platform/kernel/u-boot.git] / include / configs / kmcent2.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2016 Keymile AG
4  * Rainer Boschung <rainer.boschung@keymile.com>
5  *
6  */
7
8 #ifndef __KMCENT2_H
9 #define __KMCENT2_H
10
11 #define CONFIG_HOSTNAME         "kmcent2"
12 #define KM_BOARD_NAME   CONFIG_HOSTNAME
13
14 /*
15  * The Linux fsl_fman driver needs to be able to process frames with more
16  * than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot
17  * parameters
18  */
19 #define CONFIG_KM_DEF_BOOT_ARGS_CPU     "fsl_dpaa_fman.fsl_fm_max_frm=1558"
20
21 #include "km/keymile-common.h"
22
23 /* Application IFC chip selects */
24 #define SYS_LAWAPP_BASE         0xc0000000
25 #define SYS_LAWAPP_BASE_PHYS    (0xf00000000ull | SYS_LAWAPP_BASE)
26
27 /* Application IFC CS4 MRAM */
28 #define CONFIG_SYS_MRAM_BASE            SYS_LAWAPP_BASE
29 #define SYS_MRAM_BASE_PHYS      SYS_LAWAPP_BASE_PHYS
30 #define SYS_MRAM_CSPR_EXT       (0x0f)
31 #define SYS_MRAM_CSPR   (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \
32                                 CSPR_PORT_SIZE_8 | /* 8 bit */          \
33                                 CSPR_MSEL_GPCM   | /* msel = gpcm */    \
34                                 CSPR_V /* bank is valid */)
35 #define SYS_MRAM_AMASK          IFC_AMASK(2 * 1024 * 1024) /* 2 MiB */
36 #define SYS_MRAM_CSOR           CSOR_GPCM_TRHZ_40
37 /* MRAM Timing parameters for IFC CS4 */
38 #define SYS_MRAM_FTIM0  (FTIM0_GPCM_TACSE(0x6) | \
39                         FTIM0_GPCM_TEADC(0x8)  | \
40                         FTIM0_GPCM_TEAHC(0x2))
41 #define SYS_MRAM_FTIM1  (FTIM1_GPCM_TACO(0x2) | \
42                         FTIM1_GPCM_TRAD(0xe))
43 #define SYS_MRAM_FTIM2  (FTIM2_GPCM_TCS(0x2) | \
44                         FTIM2_GPCM_TCH(0x2)  | \
45                         FTIM2_GPCM_TWP(0x8))
46 #define SYS_MRAM_FTIM3  0x04000000
47 #define CONFIG_SYS_CSPR4_EXT    SYS_MRAM_CSPR_EXT
48 #define CONFIG_SYS_CSPR4        SYS_MRAM_CSPR
49 #define CONFIG_SYS_AMASK4       SYS_MRAM_AMASK
50 #define CONFIG_SYS_CSOR4        SYS_MRAM_CSOR
51 #define CONFIG_SYS_CS4_FTIM0    SYS_MRAM_FTIM0
52 #define CONFIG_SYS_CS4_FTIM1    SYS_MRAM_FTIM1
53 #define CONFIG_SYS_CS4_FTIM2    SYS_MRAM_FTIM2
54 #define CONFIG_SYS_CS4_FTIM3    SYS_MRAM_FTIM3
55
56 /* Application IFC CS6: BFTIC */
57 #define SYS_BFTIC_BASE          0xd0000000
58 #define SYS_BFTIC_BASE_PHYS     (0xf00000000ull | SYS_BFTIC_BASE)
59 #define SYS_BFTIC_CSPR_EXT      (0x0f)
60 #define SYS_BFTIC_CSPR  (CSPR_PHYS_ADDR(SYS_BFTIC_BASE) | \
61                                 CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
62                                 CSPR_MSEL_GPCM |   /* MSEL = GPCM */\
63                                 CSPR_V)            /* valid */
64 #define SYS_BFTIC_AMASK IFC_AMASK(64 * 1024)  /* 64kB */
65 #define SYS_BFTIC_CSOR  CSOR_GPCM_TRHZ_40
66 /* BFTIC Timing parameters for IFC CS6 */
67 #define SYS_BFTIC_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
68                                 FTIM0_GPCM_TEADC(0x8) | \
69                                 FTIM0_GPCM_TEAHC(0x2))
70 #define SYS_BFTIC_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
71                                 FTIM1_GPCM_TRAD(0x12))
72 #define SYS_BFTIC_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
73                                 FTIM2_GPCM_TCH(0x1) | \
74                                 FTIM2_GPCM_TWP(0x12))
75 #define SYS_BFTIC_FTIM3 0x04000000
76 #define CONFIG_SYS_CSPR6_EXT    SYS_BFTIC_CSPR_EXT
77 #define CONFIG_SYS_CSPR6        SYS_BFTIC_CSPR
78 #define CONFIG_SYS_AMASK6       SYS_BFTIC_AMASK
79 #define CONFIG_SYS_CSOR6        SYS_BFTIC_CSOR
80 #define CONFIG_SYS_CS6_FTIM0    SYS_BFTIC_FTIM0
81 #define CONFIG_SYS_CS6_FTIM1    SYS_BFTIC_FTIM1
82 #define CONFIG_SYS_CS6_FTIM2    SYS_BFTIC_FTIM2
83 #define CONFIG_SYS_CS6_FTIM3    SYS_BFTIC_FTIM3
84
85 /* Application IFC CS7 PAXE */
86 #define CONFIG_SYS_PAXE_BASE            0xd8000000
87 #define SYS_PAXE_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_PAXE_BASE)
88 #define SYS_PAXE_CSPR_EXT       (0x0f)
89 #define SYS_PAXE_CSPR  (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \
90                                 CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
91                                 CSPR_MSEL_GPCM |   /* MSEL = GPCM */\
92                                 CSPR_V)            /* valid */
93 #define SYS_PAXE_AMASK IFC_AMASK(64 * 1024)  /* 64kB */
94 #define SYS_PAXE_CSOR  CSOR_GPCM_TRHZ_40
95 /* PAXE Timing parameters for IFC CS7 */
96 #define SYS_PAXE_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
97                         FTIM0_GPCM_TEADC(0x8) | \
98                         FTIM0_GPCM_TEAHC(0x2))
99 #define SYS_PAXE_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
100                         FTIM1_GPCM_TRAD(0x12))
101 #define SYS_PAXE_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
102                         FTIM2_GPCM_TCH(0x1) | \
103                         FTIM2_GPCM_TWP(0x12))
104 #define SYS_PAXE_FTIM3  0x04000000
105 #define CONFIG_SYS_CSPR7_EXT    SYS_PAXE_CSPR_EXT
106 #define CONFIG_SYS_CSPR7        SYS_PAXE_CSPR
107 #define CONFIG_SYS_AMASK7       SYS_PAXE_AMASK
108 #define CONFIG_SYS_CSOR7        SYS_PAXE_CSOR
109 #define CONFIG_SYS_CS7_FTIM0    SYS_PAXE_FTIM0
110 #define CONFIG_SYS_CS7_FTIM1    SYS_PAXE_FTIM1
111 #define CONFIG_SYS_CS7_FTIM2    SYS_PAXE_FTIM2
112 #define CONFIG_SYS_CS7_FTIM3    SYS_PAXE_FTIM3
113
114 /* PRST */
115 #define KM_BFTIC4_RST           0
116 #define KM_DPAXE_RST            1
117 #define KM_FEMT_RST             3
118 #define KM_FOAM_RST             4
119 #define KM_EFE_RST              5
120 #define KM_ES_PHY_RST           6
121 #define KM_XES_PHY_RST          7
122 #define KM_ZL30158_RST          8
123 #define KM_ZL30364_RST          9
124 #define KM_BOBCAT_RST           10
125 #define KM_ETHSW_DDR_RST                12
126 #define KM_CFE_RST              13
127 #define KM_PEXSW_RST            14
128 #define KM_PEXSW_NT_RST         15
129
130 /* QRIO GPIOs used for deblocking */
131 #define KM_I2C_DEBLOCK_PORT     QRIO_GPIO_A
132 #define KM_I2C_DEBLOCK_SCL      20
133 #define KM_I2C_DEBLOCK_SDA      21
134
135 /* High Level Configuration Options */
136 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
137 #define CONFIG_FSL_CORENET              /* Freescale CoreNet platform */
138
139 #define CONFIG_RESET_VECTOR_ADDRESS     0xebfffffc
140
141 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
142 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
143 #define CONFIG_PCIE1                    /* PCIE controller 1 */
144
145 /* Environment in parallel NOR-Flash */
146 #define CONFIG_ENV_TOTAL_SIZE           0x040000
147 #define ENV_DEL_ADDR            0xebf00000      /*direct for newenv*/
148
149 /*
150  * These can be toggled for performance analysis, otherwise use default.
151  */
152 #define CONFIG_SYS_CACHE_STASHING
153 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
154
155 /* POST memory regions test */
156 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS
157
158 /*
159  *  Config the L3 Cache as L3 SRAM
160  */
161 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
162 #define CONFIG_SYS_L3_SIZE              256 << 10
163
164 #define CONFIG_SYS_DCSRBAR              0xf0000000
165 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
166
167 /*
168  * DDR Setup
169  */
170 #define CONFIG_VERY_BIG_RAM
171 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
172 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
173
174 #define SPD_EEPROM_ADDRESS      0x54
175 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
176
177 /******************************************************************************
178  * (PRAM usage)
179  * ... -------------------------------------------------------
180  * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
181  * ... |<------------------- pram -------------------------->|
182  * ... -------------------------------------------------------
183  * @END_OF_RAM:
184  * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
185  * @CONFIG_KM_PHRAM: address for /var
186  * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
187  * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
188  */
189
190 /* size of rootfs in RAM */
191 #define CONFIG_KM_ROOTFSSIZE    0x0
192 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
193  * is not valid yet, which is the case for when u-boot copies itself to RAM
194  */
195 #define CONFIG_PRAM             ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
196
197 /*
198  * IFC Definitions
199  */
200 /* NOR flash on IFC CS0 */
201 #define CONFIG_SYS_FLASH_BASE           0xe8000000
202 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | \
203                                         CONFIG_SYS_FLASH_BASE)
204
205 #define CONFIG_SYS_NOR_CSPR_EXT (0x0f)
206 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
207                                 CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\
208                                 0x00000010 |        /* drive TE high */\
209                                 CSPR_MSEL_NOR |     /* MSEL = NOR */\
210                                 CSPR_V)             /* valid */
211 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(64 * 1024 * 1024) /* 64MB */
212 #define CONFIG_SYS_NOR_CSOR     (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\
213                                 CSOR_NOR_TRHZ_20 | \
214                                 CSOR_NOR_BCTLD)
215
216 /* NOR Flash Timing Params */
217 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
218                                 FTIM0_NOR_TEADC(0x7) | \
219                                 FTIM0_NOR_TEAHC(0x1))
220 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
221                                 FTIM1_NOR_TRAD_NOR(0x21) | \
222                                 FTIM1_NOR_TSEQRAD_NOR(0x21))
223 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCH(0x1) | \
224                                 FTIM2_NOR_TCS(0x1) | \
225                                 FTIM2_NOR_TWP(0xb) | \
226                                 FTIM2_NOR_TWPH(0x6))
227 #define CONFIG_SYS_NOR_FTIM3    0x0
228
229 #define CONFIG_SYS_CSPR0_EXT    CONFIG_SYS_NOR_CSPR_EXT
230 #define CONFIG_SYS_CSPR0        CONFIG_SYS_NOR_CSPR
231 #define CONFIG_SYS_AMASK0       CONFIG_SYS_NOR_AMASK
232 #define CONFIG_SYS_CSOR0        CONFIG_SYS_NOR_CSOR
233 #define CONFIG_SYS_CS0_FTIM0    CONFIG_SYS_NOR_FTIM0
234 #define CONFIG_SYS_CS0_FTIM1    CONFIG_SYS_NOR_FTIM1
235 #define CONFIG_SYS_CS0_FTIM2    CONFIG_SYS_NOR_FTIM2
236 #define CONFIG_SYS_CS0_FTIM3    CONFIG_SYS_NOR_FTIM3
237
238 /* More NOR Flash params */
239 #define CONFIG_SYS_FLASH_QUIET_TEST
240
241 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
242
243 #define CONFIG_SYS_FLASH_EMPTY_INFO
244 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
245
246 /* NAND Flash on IFC CS1*/
247 #define CONFIG_SYS_NAND_BASE            0xfa000000
248 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
249
250 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0f)
251 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
252                                 CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\
253                                 0x00000010 |       /* drive TE high */\
254                                 CSPR_MSEL_NAND |   /* MSEL = NAND */\
255                                 CSPR_V)            /* valid */
256 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024) /* 64kB */
257
258 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
259                                 CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */   \
260                                 CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */        \
261                                 CSOR_NAND_RAL_3      | /* RAL = 3Bytes */     \
262                                 CSOR_NAND_PGS_2K     | /* Page size = 2K */   \
263                                 CSOR_NAND_SPRZ_128   | /* Spare size = 128 */ \
264                                 CSOR_NAND_PB(64)     | /* 64 Pages/Block */   \
265                                 CSOR_NAND_TRHZ_40    | /**/                   \
266                                 CSOR_NAND_BCTLD)       /**/
267
268 /* ONFI NAND Flash mode0 Timing Params */
269 #define CONFIG_SYS_NAND_FTIM0   (FTIM0_NAND_TCCST(0x3) | \
270                                 FTIM0_NAND_TWP(0x8) | \
271                                 FTIM0_NAND_TWCHT(0x3) | \
272                                 FTIM0_NAND_TWH(0x5))
273 #define CONFIG_SYS_NAND_FTIM1   (FTIM1_NAND_TADLE(0x1e) | \
274                                 FTIM1_NAND_TWBE(0x1e) | \
275                                 FTIM1_NAND_TRR(0x6) | \
276                                 FTIM1_NAND_TRP(0x8))
277 #define CONFIG_SYS_NAND_FTIM2   (FTIM2_NAND_TRAD(0x9) | \
278                                 FTIM2_NAND_TREH(0x5) | \
279                                 FTIM2_NAND_TWHRE(0x3c))
280 #define CONFIG_SYS_NAND_FTIM3   (FTIM3_NAND_TWW(0x1e))
281
282 #define CONFIG_SYS_CSPR1_EXT    CONFIG_SYS_NAND_CSPR_EXT
283 #define CONFIG_SYS_CSPR1        CONFIG_SYS_NAND_CSPR
284 #define CONFIG_SYS_AMASK1       CONFIG_SYS_NAND_AMASK
285 #define CONFIG_SYS_CSOR1        CONFIG_SYS_NAND_CSOR
286 #define CONFIG_SYS_CS1_FTIM0    CONFIG_SYS_NAND_FTIM0
287 #define CONFIG_SYS_CS1_FTIM1    CONFIG_SYS_NAND_FTIM1
288 #define CONFIG_SYS_CS1_FTIM2    CONFIG_SYS_NAND_FTIM2
289 #define CONFIG_SYS_CS1_FTIM3    CONFIG_SYS_NAND_FTIM3
290
291 /* More NAND Flash Params */
292 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
293 #define CONFIG_SYS_MAX_NAND_DEVICE      1
294
295 /* QRIO on IFC CS2 */
296 #define CONFIG_SYS_QRIO_BASE            0xfb000000
297 #define CONFIG_SYS_QRIO_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_QRIO_BASE)
298 #define SYS_QRIO_CSPR_EXT       (0x0f)
299 #define SYS_QRIO_CSPR   (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
300                                 CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
301                                 0x00000010 |       /* drive TE high */\
302                                 CSPR_MSEL_GPCM |   /* MSEL = GPCM */\
303                                 CSPR_V)           /* valid */
304 #define SYS_QRIO_AMASK  IFC_AMASK(64 * 1024)  /* 64kB */
305 #define SYS_QRIO_CSOR   (CSOR_GPCM_TRHZ_20 |\
306                         CSOR_GPCM_BCTLD)
307 /* QRIO Timing parameters for IFC CS2 */
308 #define SYS_QRIO_FTIM0  (FTIM0_GPCM_TACSE(0x2) | \
309                         FTIM0_GPCM_TEADC(0x8) | \
310                         FTIM0_GPCM_TEAHC(0x2))
311 #define SYS_QRIO_FTIM1  (FTIM1_GPCM_TACO(0x2) | \
312                         FTIM1_GPCM_TRAD(0x6))
313 #define SYS_QRIO_FTIM2  (FTIM2_GPCM_TCS(0x1) | \
314                         FTIM2_GPCM_TCH(0x1) | \
315                         FTIM2_GPCM_TWP(0x7))
316 #define SYS_QRIO_FTIM3  0x04000000
317 #define CONFIG_SYS_CSPR2_EXT    SYS_QRIO_CSPR_EXT
318 #define CONFIG_SYS_CSPR2        SYS_QRIO_CSPR
319 #define CONFIG_SYS_AMASK2       SYS_QRIO_AMASK
320 #define CONFIG_SYS_CSOR2        SYS_QRIO_CSOR
321 #define CONFIG_SYS_CS2_FTIM0    SYS_QRIO_FTIM0
322 #define CONFIG_SYS_CS2_FTIM1    SYS_QRIO_FTIM1
323 #define CONFIG_SYS_CS2_FTIM2    SYS_QRIO_FTIM2
324 #define CONFIG_SYS_CS2_FTIM3    SYS_QRIO_FTIM3
325
326 #define CONFIG_HWCONFIG
327
328 /* define to use L1 as initial stack */
329 #define CONFIG_SYS_INIT_RAM_LOCK
330 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
331 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
332 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
333 /* The assembler doesn't like typecast */
334 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
335         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
336           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
337 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
338
339 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
340
341 #define CONFIG_SYS_MONITOR_LEN          0xc0000         /* 768k */
342
343 /*
344  * Serial Port - controlled on board with jumper J8
345  * open - index 2
346  * shorted - index 1
347  * Retain non-DM serial port for debug purposes.
348  */
349 #if !defined(CONFIG_DM_SERIAL)
350 #define CONFIG_SYS_NS16550_SERIAL
351 #define CONFIG_SYS_NS16550_REG_SIZE     1
352 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
353 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
354 #endif
355
356 #ifndef __ASSEMBLY__
357 void set_sda(int state);
358 void set_scl(int state);
359 int get_sda(void);
360 int get_scl(void);
361 #endif
362
363 /*
364  * General PCI
365  * Memory space is mapped 1-1, but I/O space must start from 0.
366  */
367 /* controller 1 */
368 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
369 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
370 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
371 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
372
373 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
374 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
375 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
376 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
377 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
378 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
379 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
380                                         CONFIG_SYS_BMAN_CENA_SIZE)
381 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
382 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
383 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
384 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
385 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
386 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
387 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
388 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
389 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
390                                         CONFIG_SYS_QMAN_CENA_SIZE)
391 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
392 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
393
394 #define CONFIG_SYS_DPAA_FMAN
395 #define CONFIG_SYS_DPAA_PME
396
397 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
398
399 /* Qman / Bman */
400 /* RGMII (FM1@DTESC5) is local managemant interface */
401 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x11
402
403 /*
404  * Hardware Watchdog
405  */
406 #define CONFIG_WATCHDOG_PRESC 34        /* wdog prescaler 2^(64-34) ~10min */
407 #define CONFIG_WATCHDOG_RC WRC_CHIP     /* reset chip on watchdog event */
408
409 /*
410  * For booting Linux, the board info and command line data
411  * have to be in the first 64 MB of memory, since this is
412  * the maximum mapped by the Linux kernel during initialization.
413  */
414 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
415 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
416
417 /*
418  * Environment Configuration
419  */
420 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
421 #define CONFIG_KM_DEF_ENV
422 #endif
423
424 #define __USB_PHY_TYPE  utmi
425
426 #define CONFIG_KM_DEF_ENV_CPU                                           \
427         "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"                   \
428         "cramfsloadfdt="                                                \
429                 "cramfsload ${fdt_addr_r} "                             \
430                 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"             \
431         "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"               \
432         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
433                 " +${filesize} && "                                     \
434                 "erase " __stringify(CONFIG_SYS_MONITOR_BASE)           \
435                 " +${filesize} && "                                     \
436                 "cp.b ${load_addr_r} "                                  \
437                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
438                 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
439                 " +${filesize}\0"                                       \
440         "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE)    \
441                 " +${filesize} && "                                     \
442                 "erase " __stringify(CONFIG_SYS_FLASH_BASE)             \
443                 " +${filesize} && "                                     \
444                 "cp.b ${load_addr_r} "                                  \
445                 __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && "   \
446                 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
447                 " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0"           \
448         "set_fdthigh=true\0"                                            \
449         "checkfdt=true\0"                                               \
450         "fpgacfg=true\0"                                                \
451         ""
452
453 #define CONFIG_HW_ENV_SETTINGS                                          \
454         "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0"                       \
455         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
456         "usb_dr_mode=host\0"
457
458 #define CONFIG_KM_NEW_ENV                                               \
459         "newenv=protect off " __stringify(ENV_DEL_ADDR)                 \
460                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "          \
461                 "erase " __stringify(ENV_DEL_ADDR)                      \
462                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "          \
463                 "protect on " __stringify(ENV_DEL_ADDR)                 \
464                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
465
466 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
467 #ifndef CONFIG_KM_DEF_ARCH
468 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
469 #endif
470
471 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
472         CONFIG_KM_DEF_ENV                                               \
473         CONFIG_KM_DEF_ARCH                                              \
474         CONFIG_KM_NEW_ENV                                               \
475         CONFIG_HW_ENV_SETTINGS                                          \
476         "EEprom_ivm=pca9547:70:9\0"                                     \
477         ""
478
479 #endif  /* __KMCENT2_H */