3 * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
4 * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 /* KMBEC FPGA (PRIO) */
13 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
14 #define CONFIG_SYS_KMBEC_FPGA_SIZE 64
16 #if defined CONFIG_KMETER1
17 #define CONFIG_HOSTNAME "kmeter1"
18 #define CONFIG_KM_BOARD_NAME "kmeter1"
19 #define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
20 #elif defined CONFIG_KMCOGE5NE
21 #define CONFIG_HOSTNAME "kmcoge5ne"
22 #define CONFIG_KM_BOARD_NAME "kmcoge5ne"
23 #define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
24 #define CONFIG_NAND_ECC_BCH
25 #define CONFIG_NAND_KMETER1
26 #define CONFIG_SYS_MAX_NAND_DEVICE 1
27 #define NAND_MAX_CHIPS 1
28 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
30 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
31 #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
33 #error ("Board not supported")
37 * High Level Configuration Options
39 #define CONFIG_QE /* Has QE */
40 #define CONFIG_MPC8360 /* MPC8360 CPU specific */
42 /* include common defines/options for all 83xx Keymile boards */
43 #include "km/km83xx-common.h"
48 #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
51 * Hardware Reset Configuration Word
53 #define CONFIG_SYS_HRCW_LOW (\
54 HRCWL_CSB_TO_CLKIN_4X1 | \
55 HRCWL_CORE_TO_CSB_2X1 | \
56 HRCWL_CE_PLL_VCO_DIV_2 | \
59 #define CONFIG_SYS_HRCW_HIGH (\
61 HRCWH_FROM_0X00000100 | \
62 HRCWH_BOOTSEQ_DISABLE | \
63 HRCWH_SW_WATCHDOG_DISABLE | \
64 HRCWH_ROM_LOC_LOCAL_16BIT | \
72 #define CONFIG_SYS_DDR_SDRAM_CFG (\
73 SDRAM_CFG_SDRAM_TYPE_DDR2 | \
77 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
79 #ifdef CONFIG_KMCOGE5NE
81 * KMCOGE5NE has 512 MB RAM
83 #define CONFIG_SYS_DDR_CS0_CONFIG (\
86 CSCONFIG_ODT_WR_ONLY_CURRENT | \
87 CSCONFIG_BANK_BIT_3 | \
88 CSCONFIG_ROW_BIT_13 | \
91 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
92 CSCONFIG_ROW_BIT_13 | \
93 CSCONFIG_COL_BIT_10 | \
94 CSCONFIG_ODT_WR_ONLY_CURRENT)
97 #define CONFIG_SYS_DDR_CLK_CNTL (\
98 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
100 #define CONFIG_SYS_DDR_INTERVAL (\
101 (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
102 (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
104 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
106 #define CONFIG_SYS_DDRCDR (\
109 #define CONFIG_SYS_DDR_MODE 0x47860452
110 #define CONFIG_SYS_DDR_MODE2 0x8080c000
112 #define CONFIG_SYS_DDR_TIMING_0 (\
113 (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
114 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
115 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
116 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
117 (0 << TIMING_CFG0_WWT_SHIFT) | \
118 (0 << TIMING_CFG0_RRT_SHIFT) | \
119 (0 << TIMING_CFG0_WRT_SHIFT) | \
120 (0 << TIMING_CFG0_RWT_SHIFT))
122 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
123 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
124 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
125 (3 << TIMING_CFG1_WRREC_SHIFT) | \
126 (7 << TIMING_CFG1_REFREC_SHIFT) | \
127 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
128 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
129 (3 << TIMING_CFG1_PRETOACT_SHIFT))
131 #define CONFIG_SYS_DDR_TIMING_2 (\
132 (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
133 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
134 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
135 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
136 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
137 (5 << TIMING_CFG2_CPO_SHIFT) | \
138 (0 << TIMING_CFG2_ADD_LAT_SHIFT))
140 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
143 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
146 * Local Bus Configuration & Clock Setup
148 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
149 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
150 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
153 * PAXE on the local bus CS3
155 #define CONFIG_SYS_PAXE_BASE 0xA0000000
156 #define CONFIG_SYS_PAXE_SIZE 256
158 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
160 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
162 #define CONFIG_SYS_BR3_PRELIM (\
163 CONFIG_SYS_PAXE_BASE | \
164 (1 << BR_PS_SHIFT) | \
167 #define CONFIG_SYS_OR3_PRELIM (\
168 MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
175 #ifdef CONFIG_KMCOGE5NE
177 * BFTIC3 on the local bus CS4
179 #define CONFIG_SYS_BFTIC3_BASE 0xB0000000
180 #define CONFIG_SYS_BFTIC3_SIZE 256
182 #define CONFIG_SYS_BR4_PRELIM (\
183 CONFIG_SYS_BFTIC3_BASE |\
184 (1 << BR_PS_SHIFT) | \
187 #define CONFIG_SYS_OR4_PRELIM (\
188 MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
200 /* PAXE: icache cacheable, but dcache-inhibit and guarded */
201 #define CONFIG_SYS_IBAT5L (\
202 CONFIG_SYS_PAXE_BASE | \
206 #define CONFIG_SYS_IBAT5U (\
207 CONFIG_SYS_PAXE_BASE | \
212 #define CONFIG_SYS_DBAT5L (\
213 CONFIG_SYS_PAXE_BASE | \
215 BATL_CACHEINHIBIT | \
218 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
220 #ifdef CONFIG_KMCOGE5NE
221 /* BFTIC3: icache cacheable, but dcache-inhibit and guarded */
222 #define CONFIG_SYS_IBAT6L (\
223 CONFIG_SYS_BFTIC3_BASE | \
227 #define CONFIG_SYS_IBAT6U (\
228 CONFIG_SYS_BFTIC3_BASE | \
233 #define CONFIG_SYS_DBAT6L (\
234 CONFIG_SYS_BFTIC3_BASE | \
236 BATL_CACHEINHIBIT | \
239 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
241 /* DDR/LBC SDRAM next 256M: cacheable */
242 #define CONFIG_SYS_IBAT7L (\
243 CONFIG_SYS_SDRAM_BASE2 |\
248 #define CONFIG_SYS_IBAT7U (\
249 CONFIG_SYS_SDRAM_BASE2 |\
253 /* enable POST tests */
254 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
255 #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
256 #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
257 #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
258 #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */
261 #define CONFIG_SYS_IBAT6L (0)
262 #define CONFIG_SYS_IBAT6U (0)
263 #define CONFIG_SYS_IBAT7L (0)
264 #define CONFIG_SYS_IBAT7U (0)
265 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
266 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
269 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
270 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U