include/configs/km82xx.h

   1 /*
   2  * (C) Copyright 2007-2011
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  * (easy to change)
  14  */
  15
  16 #define CONFIG_MPC8247
  17 /* MGCOGE */
  18 #if defined(CONFIG_MGCOGE)
  19 #define CONFIG_HOSTNAME         mgcoge
  20 #define CONFIG_KM_BOARD_EXTRA_ENV       ""
  21
  22 /* MGCOGE3NE */
  23 #elif defined(CONFIG_MGCOGE3NE)
  24 #define CONFIG_HOSTNAME         mgcoge3ne
  25 #define CONFIG_KM_82XX
  26 #define CONFIG_KM_BOARD_EXTRA_ENV       "bobcatreset=true\0"
  27
  28 #else
  29 #error ("Board unsupported")
  30 #endif
  31
  32 #define CONFIG_SYS_GENERIC_BOARD
  33 #define CONFIG_DISPLAY_BOARDINFO
  34
  35 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  36
  37 /* include common defines/options for all Keymile boards */
  38 #include "km/keymile-common.h"
  39 #include "km/km-powerpc.h"
  40
  41 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  42 #define CONFIG_SYS_FLASH_BASE           0xFE000000
  43 #define CONFIG_SYS_FLASH_SIZE           32
  44 #define CONFIG_SYS_FLASH_CFI
  45 #define CONFIG_FLASH_CFI_DRIVER
  46
  47 /* MGCOGE */
  48 #if defined(CONFIG_MGCOGE)
  49 #define CONFIG_SYS_MAX_FLASH_BANKS      3
  50 /* max num of sects on one chip */
  51 #define CONFIG_SYS_MAX_FLASH_SECT       512
  52
  53 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
  54 #define CONFIG_SYS_FLASH_SIZE_1 32
  55 #define CONFIG_SYS_FLASH_BASE_2 0x52000000
  56 #define CONFIG_SYS_FLASH_SIZE_2 32
  57
  58 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
  59                                         CONFIG_SYS_FLASH_BASE_1, \
  60                                         CONFIG_SYS_FLASH_BASE_2 }
  61 #define MTDIDS_DEFAULT          "nor3=app"
  62
  63 /*
  64  * Bank 1 - 60x bus SDRAM
  65  */
  66 #define SDRAM_MAX_SIZE  0x08000000                      /* max. 128 MB  */
  67 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (256 << 20)     /* less than 256 MB */
  68
  69 /* SDRAM initialization values
  70 */
  71
  72 #define CONFIG_SYS_OR1  ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
  73                            ORxS_SDAM_MSK)               |\
  74                         ORxS_BPD_8                      |\
  75                         ORxS_ROWST_PBI0_A7              |\
  76                         ORxS_NUMR_13)
  77
  78 #define CONFIG_SYS_PSDMR (                              \
  79                         PSDMR_SDAM_A14_IS_A5            |\
  80                         PSDMR_BSMA_A14_A16              |\
  81                         PSDMR_SDA10_PBI0_A9             |\
  82                         PSDMR_RFRC_5_CLK                |\
  83                         PSDMR_PRETOACT_2W               |\
  84                         PSDMR_ACTTORW_2W                |\
  85                         PSDMR_LDOTOPRE_1C               |\
  86                         PSDMR_WRC_1C                    |\
  87                         PSDMR_CL_2)
  88
  89 /* MGCOGE3NE */
  90 #elif defined(CONFIG_MGCOGE3NE)
  91 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of flash banks */
  92 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /*
  93                                                  * max num of sects on one
  94                                                  * chip
  95                                                  */
  96
  97 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
  98 #define CONFIG_SYS_FLASH_SIZE_1 128
  99
 100 #define CONFIG_SYS_FLASH_SIZE_2 0       /* dummy value to calc SYS_OR5 */
 101
 102 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
 103                                         CONFIG_SYS_FLASH_BASE_1 }
 104
 105 #define MTDIDS_DEFAULT          "nor2=app"
 106
 107 /*
 108  * Bank 1 - 60x bus SDRAM
 109  * mgcoge3ne has 256MB
 110  * mgcoge2ne has 128MB
 111  */
 112 #define SDRAM_MAX_SIZE 0x10000000                       /* max. 256 MB  */
 113 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (512 << 20)     /* less than 512 MB */
 114
 115 #define CONFIG_SYS_OR1  ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
 116                            ORxS_SDAM_MSK)               |\
 117                         ORxS_BPD_4                      |\
 118                         ORxS_NUMR_13                    |\
 119                         ORxS_IBID)
 120
 121 #define CONFIG_SYS_PSDMR (                              \
 122                         PSDMR_PBI                       |\
 123                         PSDMR_RFEN                      |\
 124                         PSDMR_BSMA_A13_A15              |\
 125                         PSDMR_RFRC_5_CLK                |\
 126                         PSDMR_PRETOACT_2W               |\
 127                         PSDMR_ACTTORW_2W                |\
 128                         PSDMR_LDOTOPRE_1C               |\
 129                         PSDMR_WRC_1C                    |\
 130                         PSDMR_CL_2)
 131
 132 #define CONFIG_SYS_SDRAM_LIST   {                                       \
 133         {       .size   = 256 << 20,                                    \
 134                 .or1    = ORxS_ROWST_PBI1_A4,                           \
 135                 .psdmr  = PSDMR_SDAM_A17_IS_A5 | PSDMR_SDA10_PBI1_A6,   \
 136         },                                                              \
 137         {       .size   = 128 << 20,                                    \
 138                 .or1    = ORxS_ROWST_PBI1_A5,                           \
 139                 .psdmr  = PSDMR_SDAM_A16_IS_A5 | PSDMR_SDA10_PBI1_A7,   \
 140         },                                                              \
 141 }
 142 #endif /* defined(CONFIG_MGCOGE3NE) */
 143
 144 /* include further common stuff for all keymile 82xx boards */
 145 /*
 146  * Select serial console configuration
 147  *
 148  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 149  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 150  * for SCC).
 151  */
 152 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
 153 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
 154 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
 155 #define CONFIG_CONS_INDEX       2       /* SMC2 is used for console  */
 156 #define CONFIG_SYS_SMC_RXBUFLEN 128
 157 #define CONFIG_SYS_MAXIDLE      10
 158
 159 /*
 160  * Select ethernet configuration
 161  *
 162  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
 163  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
 164  * SCC, 1-3 for FCC)
 165  *
 166  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
 167  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
 168  * must be unset.
 169  */
 170 #define CONFIG_ETHER_ON_SCC             /* Ethernet is on SCC */
 171 #undef  CONFIG_ETHER_ON_FCC             /* Ethernet is not on FCC     */
 172 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
 173
 174 #define CONFIG_ETHER_INDEX      4
 175 #define CONFIG_HAS_ETH0
 176 #define CONFIG_SYS_SCC_TOUT_LOOP        10000000
 177
 178 #define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
 179
 180 #ifndef CONFIG_8260_CLKIN
 181 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 182 #endif
 183
 184 #define BOOTFLASH_START         0xFE000000
 185
 186 #define CONFIG_KM_CONSOLE_TTY   "ttyCPM0"
 187
 188 #define MTDPARTS_DEFAULT        "mtdparts="                             \
 189         "app:"                                                          \
 190                 "768k(u-boot),"                                         \
 191                 "128k(env),"                                            \
 192                 "128k(envred),"                                         \
 193                 "3072k(free),"                                          \
 194                 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")"
 195
 196 /*
 197  * Default environment settings
 198  */
 199 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 200         CONFIG_KM_BOARD_EXTRA_ENV                                       \
 201         CONFIG_KM_DEF_ENV                                               \
 202         "unlock=yes\0"                                                  \
 203         "newenv="                                                       \
 204                 "prot off 0xFE0C0000 +0x40000 && "                      \
 205                 "era 0xFE0C0000 +0x40000\0"                             \
 206         "arch=ppc_82xx\0"                                       \
 207         ""
 208
 209 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 210 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 211 #define CONFIG_SYS_RAMBOOT
 212 #endif
 213
 214 #define CONFIG_SYS_MONITOR_LEN          (768 << 10)
 215
 216 #define CONFIG_ENV_IS_IN_FLASH
 217
 218 #ifdef CONFIG_ENV_IS_IN_FLASH
 219 #define CONFIG_ENV_SECT_SIZE    0x20000
 220 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 221                                         CONFIG_SYS_MONITOR_LEN)
 222 #define CONFIG_ENV_OFFSET       CONFIG_SYS_MONITOR_LEN
 223
 224 /* Address and size of Redundant Environment Sector     */
 225 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 226                                                 CONFIG_ENV_SECT_SIZE)
 227 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
 228 #endif /* CONFIG_ENV_IS_IN_FLASH */
 229
 230 /* enable I2C and select the hardware/software driver */
 231 #define CONFIG_SYS_I2C
 232 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 233 #define CONFIG_SYS_I2C_INIT_BOARD
 234 #define CONFIG_SYS_NUM_I2C_BUSES        3
 235 #define CONFIG_SYS_I2C_MAX_HOPS         1
 236 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 237 #define CONFIG_SYS_I2C_SPEED            CONFIG_SYS_I2C_SOFT_SPEED
 238 #define CONFIG_SYS_I2C_SOFT_SLAVE       0x7F
 239 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 240                         {0, {{I2C_MUX_PCA9542, 0x70, 0} } }, \
 241                         {0, {{I2C_MUX_PCA9542, 0x70, 1} } } }
 242
 243 #define CONFIG_KM_IVM_BUS               1       /* I2C2 (Mux-Port 1)*/
 244 #define CONFIG_KM_I2C_ABORT
 245
 246 /*
 247  * Software (bit-bang) I2C driver configuration
 248  */
 249
 250 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 251 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 252 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 253 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 254 #define I2C_SDA(bit)    do { \
 255                                 if (bit) \
 256                                         iop->pdat |=  0x00010000; \
 257                                 else \
 258                                         iop->pdat &= ~0x00010000; \
 259                         } while (0)
 260 #define I2C_SCL(bit)    do { \
 261                                 if (bit) \
 262                                         iop->pdat |=  0x00020000; \
 263                                 else \
 264                                         iop->pdat &= ~0x00020000; \
 265                         } while (0)
 266 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 267
 268 #ifndef __ASSEMBLY__
 269 void set_sda(int state);
 270 void set_scl(int state);
 271 int get_sda(void);
 272 int get_scl(void);
 273 #endif
 274
 275 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 276 #define CONFIG_DTT_LM75                 /* ON Semi's LM75               */
 277 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
 278 #define CONFIG_SYS_DTT_MAX_TEMP 70
 279 #define CONFIG_SYS_DTT_HYSTERESIS       3
 280 #define CONFIG_SYS_DTT_BUS_NUM          2
 281
 282 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 283
 284 #define CONFIG_SYS_IMMR         0xF0000000
 285
 286 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 287 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000 /* used size in DPRAM */
 288 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 289                                                 GENERATED_GBL_DATA_SIZE)
 290 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 291
 292 /* Hard reset configuration word */
 293 #define CONFIG_SYS_HRCW_MASTER          0x0604b211
 294
 295 /* No slaves */
 296 #define CONFIG_SYS_HRCW_SLAVE1          0
 297 #define CONFIG_SYS_HRCW_SLAVE2          0
 298 #define CONFIG_SYS_HRCW_SLAVE3          0
 299 #define CONFIG_SYS_HRCW_SLAVE4          0
 300 #define CONFIG_SYS_HRCW_SLAVE5          0
 301 #define CONFIG_SYS_HRCW_SLAVE6          0
 302 #define CONFIG_SYS_HRCW_SLAVE7          0
 303
 304 /* Initial Memory map for Linux */
 305 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 306
 307 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
 308 #if defined(CONFIG_CMD_KGDB)
 309 #  define CONFIG_SYS_CACHELINE_SHIFT    5 /* log base 2 of the above value */
 310 #endif
 311
 312 #define CONFIG_SYS_HID0_INIT            0
 313 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
 314
 315 #define CONFIG_SYS_HID2         0
 316
 317 #define CONFIG_SYS_SIUMCR               0x4020c200
 318 #define CONFIG_SYS_SYPCR                0xFFFFFF83
 319 #define CONFIG_SYS_BCR                  0x10000000
 320 #define CONFIG_SYS_SCCR         (SCCR_PCI_MODE | SCCR_PCI_MODCK)
 321
 322 /*
 323  *-----------------------------------------------------------------------
 324  * RMR - Reset Mode Register                                     5-5
 325  *-----------------------------------------------------------------------
 326  * turn on Checkstop Reset Enable
 327  */
 328 #define CONFIG_SYS_RMR         0
 329
 330 /*
 331  *-----------------------------------------------------------------------
 332  * TMCNTSC - Time Counter Status and Control                     4-40
 333  *-----------------------------------------------------------------------
 334  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 335  * and enable Time Counter
 336  */
 337 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 338
 339 /*
 340  *-----------------------------------------------------------------------
 341  * PISCR - Periodic Interrupt Status and Control                 4-42
 342  *-----------------------------------------------------------------------
 343  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 344  * Periodic timer
 345  */
 346 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 347
 348 /*
 349  *-----------------------------------------------------------------------
 350  * RCCR - RISC Controller Configuration                         13-7
 351  *-----------------------------------------------------------------------
 352  */
 353 #define CONFIG_SYS_RCCR        0
 354
 355 /*
 356  * Init Memory Controller:
 357  *
 358  * Bank Bus     Machine PortSz  Device
 359  * ---- ---     ------- ------  ------
 360  *  0   60x     GPCM     8 bit  FLASH
 361  *  1   60x     SDRAM   32 bit  SDRAM
 362  *  3   60x     GPCM     8 bit  GPIO/PIGGY
 363  *  5   60x     GPCM    16 bit  CFG-Flash
 364  *
 365  */
 366 /* Bank 0 - FLASH
 367  */
 368 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)    |\
 369                          BRx_PS_8                       |\
 370                          BRx_MS_GPCM_P                  |\
 371                          BRx_V)
 372
 373 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)        |\
 374                          ORxG_CSNT                      |\
 375                          ORxG_ACS_DIV2                  |\
 376                          ORxG_SCY_5_CLK                 |\
 377                          ORxG_TRLX)
 378
 379 #define CONFIG_SYS_MPTPR       0x1800
 380
 381 /*
 382  *-----------------------------------------------------------------------------
 383  * Address for Mode Register Set (MRS) command
 384  *-----------------------------------------------------------------------------
 385  */
 386 #define CONFIG_SYS_MRS_OFFS     0x00000110
 387 #define CONFIG_SYS_PSRT        0x0e
 388
 389 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
 390                          BRx_PS_64              |\
 391                          BRx_MS_SDRAM_P         |\
 392                          BRx_V)
 393
 394 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1
 395
 396 /*
 397  * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
 398  */
 399 #define CONFIG_SYS_KMBEC_FPGA_BASE      0x30000000
 400 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 401
 402 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
 403                          BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 404
 405 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
 406                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 407                          ORxG_SCY_3_CLK | ORxG_TRLX)
 408
 409 /*
 410  * BFTICU board FPGA on CS4 initialization values
 411  */
 412 #define CONFIG_SYS_FPGA_BASE    0x40000000
 413 #define CONFIG_SYS_FPGA_SIZE    1 /*1KB*/
 414
 415 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
 416                         BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 417
 418 #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
 419                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 420                          ORxG_SCY_3_CLK | ORxG_TRLX)
 421
 422 /*
 423  * CFG-Flash on CS5 initialization values
 424  */
 425 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
 426                          BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
 427
 428 #define CONFIG_SYS_OR5_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
 429                                  CONFIG_SYS_FLASH_SIZE_2) |\
 430                                  ORxG_CSNT | ORxG_ACS_DIV2 |\
 431                                  ORxG_SCY_5_CLK | ORxG_TRLX)
 432
 433 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC     /* "bad" address */
 434
 435 /* pass open firmware flat tree */
 436 #define CONFIG_FIT              1
 437 #define CONFIG_OF_LIBFDT        1
 438 #define CONFIG_OF_BOARD_SETUP   1
 439
 440 #define OF_TBCLK                (bd->bi_busfreq / 4)
 441 #define OF_STDOUT_PATH          "/soc/cpm/serial@11a90"
 442
 443 #endif /* __CONFIG_H */