i2c, multibus, keymile: get rid of EEprom_ivm envvariable
[platform/kernel/u-boot.git] / include / configs / km82xx.h
1 /*
2  * (C) Copyright 2007-2011
3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23
24 #ifndef __CONFIG_H
25 #define __CONFIG_H
26
27 /*
28  * High Level Configuration Options
29  * (easy to change)
30  */
31
32 #define CONFIG_MPC8247
33 /* MGCOGE */
34 #if defined(CONFIG_MGCOGE)
35 #define CONFIG_HOSTNAME         mgcoge
36 #define CONFIG_KM_BOARD_EXTRA_ENV       ""
37
38 /* MGCOGE3NE */
39 #elif defined(CONFIG_MGCOGE3NE)
40 #define CONFIG_HOSTNAME         mgcoge3ne
41 #define CONFIG_KM_82XX
42 #define CONFIG_KM_BOARD_EXTRA_ENV       "bobcatreset=true\0"
43
44 #else
45 #error ("Board unsupported")
46 #endif
47
48 #define CONFIG_SYS_TEXT_BASE    0xFE000000
49
50 /* include common defines/options for all Keymile boards */
51 #include "km/keymile-common.h"
52 #include "km/km-powerpc.h"
53
54 #define CONFIG_SYS_SDRAM_BASE           0x00000000
55 #define CONFIG_SYS_FLASH_BASE           0xFE000000
56 #define CONFIG_SYS_FLASH_SIZE           32
57 #define CONFIG_SYS_FLASH_CFI
58 #define CONFIG_FLASH_CFI_DRIVER
59
60 /* MGCOGE */
61 #if defined(CONFIG_MGCOGE)
62 #define CONFIG_SYS_MAX_FLASH_BANKS      3
63 /* max num of sects on one chip */
64 #define CONFIG_SYS_MAX_FLASH_SECT       512
65
66 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
67 #define CONFIG_SYS_FLASH_SIZE_1 32
68 #define CONFIG_SYS_FLASH_BASE_2 0x52000000
69 #define CONFIG_SYS_FLASH_SIZE_2 32
70
71 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
72                                         CONFIG_SYS_FLASH_BASE_1, \
73                                         CONFIG_SYS_FLASH_BASE_2 }
74 #define MTDIDS_DEFAULT          "nor3=app"
75
76 /*
77  * Bank 1 - 60x bus SDRAM
78  */
79 #define SDRAM_MAX_SIZE  0x08000000                      /* max. 128 MB  */
80 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (256 << 20)     /* less than 256 MB */
81
82 /* SDRAM initialization values
83 */
84
85 #define CONFIG_SYS_OR1  ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
86                            ORxS_SDAM_MSK)               |\
87                         ORxS_BPD_8                      |\
88                         ORxS_ROWST_PBI0_A7              |\
89                         ORxS_NUMR_13)
90
91 #define CONFIG_SYS_PSDMR (                              \
92                         PSDMR_SDAM_A14_IS_A5            |\
93                         PSDMR_BSMA_A14_A16              |\
94                         PSDMR_SDA10_PBI0_A9             |\
95                         PSDMR_RFRC_5_CLK                |\
96                         PSDMR_PRETOACT_2W               |\
97                         PSDMR_ACTTORW_2W                |\
98                         PSDMR_LDOTOPRE_1C               |\
99                         PSDMR_WRC_1C                    |\
100                         PSDMR_CL_2)
101
102 /* MGCOGE3NE */
103 #elif defined(CONFIG_MGCOGE3NE)
104 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of flash banks */
105 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /*
106                                                  * max num of sects on one
107                                                  * chip
108                                                  */
109
110 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
111 #define CONFIG_SYS_FLASH_SIZE_1 128
112
113 #define CONFIG_SYS_FLASH_SIZE_2 0       /* dummy value to calc SYS_OR5 */
114
115 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
116                                         CONFIG_SYS_FLASH_BASE_1 }
117
118 #define MTDIDS_DEFAULT          "nor2=app"
119
120 /*
121  * Bank 1 - 60x bus SDRAM
122  * mgcoge3ne has 256MB
123  * mgcoge2ne has 128MB
124  */
125 #define SDRAM_MAX_SIZE 0x10000000                       /* max. 256 MB  */
126 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (512 << 20)     /* less than 512 MB */
127
128 #define CONFIG_SYS_OR1  ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
129                            ORxS_SDAM_MSK)               |\
130                         ORxS_BPD_4                      |\
131                         ORxS_NUMR_13                    |\
132                         ORxS_IBID)
133
134 #define CONFIG_SYS_PSDMR (                              \
135                         PSDMR_PBI                       |\
136                         PSDMR_RFEN                      |\
137                         PSDMR_BSMA_A13_A15              |\
138                         PSDMR_RFRC_5_CLK                |\
139                         PSDMR_PRETOACT_2W               |\
140                         PSDMR_ACTTORW_2W                |\
141                         PSDMR_LDOTOPRE_1C               |\
142                         PSDMR_WRC_1C                    |\
143                         PSDMR_CL_2)
144
145 #define CONFIG_SYS_SDRAM_LIST   {                                       \
146         {       .size   = 256 << 20,                                    \
147                 .or1    = ORxS_ROWST_PBI1_A4,                           \
148                 .psdmr  = PSDMR_SDAM_A17_IS_A5 | PSDMR_SDA10_PBI1_A6,   \
149         },                                                              \
150         {       .size   = 128 << 20,                                    \
151                 .or1    = ORxS_ROWST_PBI1_A5,                           \
152                 .psdmr  = PSDMR_SDAM_A16_IS_A5 | PSDMR_SDA10_PBI1_A7,   \
153         },                                                              \
154 }
155 #endif /* defined(CONFIG_MGCOGE3NE) */
156
157 /* include further common stuff for all keymile 82xx boards */
158 /*
159  * Select serial console configuration
160  *
161  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
162  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
163  * for SCC).
164  */
165 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
166 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
167 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
168 #define CONFIG_CONS_INDEX       2       /* SMC2 is used for console  */
169 #define CONFIG_SYS_SMC_RXBUFLEN 128
170 #define CONFIG_SYS_MAXIDLE      10
171
172 /*
173  * Select ethernet configuration
174  *
175  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
176  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
177  * SCC, 1-3 for FCC)
178  *
179  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
180  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
181  * must be unset.
182  */
183 #define CONFIG_ETHER_ON_SCC             /* Ethernet is on SCC */
184 #undef  CONFIG_ETHER_ON_FCC             /* Ethernet is not on FCC     */
185 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
186
187 #define CONFIG_ETHER_INDEX      4
188 #define CONFIG_HAS_ETH0
189 #define CONFIG_SYS_SCC_TOUT_LOOP        10000000
190
191 #define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
192
193 #ifndef CONFIG_8260_CLKIN
194 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
195 #endif
196
197 #define BOOTFLASH_START         0xFE000000
198
199 #define CONFIG_KM_CONSOLE_TTY   "ttyCPM0"
200
201 #define MTDPARTS_DEFAULT        "mtdparts="                             \
202         "app:"                                                          \
203                 "768k(u-boot),"                                         \
204                 "128k(env),"                                            \
205                 "128k(envred),"                                         \
206                 "3072k(free),"                                          \
207                 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")"
208
209 /*
210  * Default environment settings
211  */
212 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
213         CONFIG_KM_BOARD_EXTRA_ENV                                       \
214         CONFIG_KM_DEF_ENV                                               \
215         "unlock=yes\0"                                                  \
216         "newenv="                                                       \
217                 "prot off 0xFE0C0000 +0x40000 && "                      \
218                 "era 0xFE0C0000 +0x40000\0"                             \
219         "arch=ppc_82xx\0"                                       \
220         ""
221
222 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
223 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
224 #define CONFIG_SYS_RAMBOOT
225 #endif
226
227 #define CONFIG_SYS_MONITOR_LEN          (768 << 10)
228
229 #define CONFIG_ENV_IS_IN_FLASH
230
231 #ifdef CONFIG_ENV_IS_IN_FLASH
232 #define CONFIG_ENV_SECT_SIZE    0x20000
233 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
234                                         CONFIG_SYS_MONITOR_LEN)
235 #define CONFIG_ENV_OFFSET       CONFIG_SYS_MONITOR_LEN
236
237 /* Address and size of Redundant Environment Sector     */
238 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
239                                                 CONFIG_ENV_SECT_SIZE)
240 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
241 #endif /* CONFIG_ENV_IS_IN_FLASH */
242
243 /* enable I2C and select the hardware/software driver */
244 #define CONFIG_SYS_I2C
245 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
246 #define CONFIG_SYS_NUM_I2C_BUSES        3
247 #define CONFIG_SYS_I2C_MAX_HOPS         1
248 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
249 #define CONFIG_SYS_I2C_SPEED            CONFIG_SYS_I2C_SOFT_SPEED
250 #define CONFIG_SYS_I2C_SOFT_SLAVE       0x7F
251 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
252                         {0, {{I2C_MUX_PCA9542, 0x70, 0} } }, \
253                         {0, {{I2C_MUX_PCA9542, 0x70, 1} } } }
254
255 #define CONFIG_KM_IVM_BUS               1       /* I2C2 (Mux-Port 1)*/
256
257 /*
258  * Software (bit-bang) I2C driver configuration
259  */
260
261 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
262 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
263 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
264 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
265 #define I2C_SDA(bit)    do { \
266                                 if (bit) \
267                                         iop->pdat |=  0x00010000; \
268                                 else \
269                                         iop->pdat &= ~0x00010000; \
270                         } while (0)
271 #define I2C_SCL(bit)    do { \
272                                 if (bit) \
273                                         iop->pdat |=  0x00020000; \
274                                 else \
275                                         iop->pdat &= ~0x00020000; \
276                         } while (0)
277 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
278
279 #ifndef __ASSEMBLY__
280 void set_sda(int state);
281 void set_scl(int state);
282 int get_sda(void);
283 int get_scl(void);
284 #endif
285
286 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
287 #define CONFIG_DTT_LM75                 /* ON Semi's LM75               */
288 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
289 #define CONFIG_SYS_DTT_MAX_TEMP 70
290 #define CONFIG_SYS_DTT_LOW_TEMP -30
291 #define CONFIG_SYS_DTT_HYSTERESIS       3
292 #define CONFIG_SYS_DTT_BUS_NUM          2
293
294 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
295
296 #define CONFIG_SYS_IMMR         0xF0000000
297
298 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
299 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000 /* used size in DPRAM */
300 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
301                                                 GENERATED_GBL_DATA_SIZE)
302 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
303
304 /* Hard reset configuration word */
305 #define CONFIG_SYS_HRCW_MASTER          0x0604b211
306
307 /* No slaves */
308 #define CONFIG_SYS_HRCW_SLAVE1          0
309 #define CONFIG_SYS_HRCW_SLAVE2          0
310 #define CONFIG_SYS_HRCW_SLAVE3          0
311 #define CONFIG_SYS_HRCW_SLAVE4          0
312 #define CONFIG_SYS_HRCW_SLAVE5          0
313 #define CONFIG_SYS_HRCW_SLAVE6          0
314 #define CONFIG_SYS_HRCW_SLAVE7          0
315
316 /* Initial Memory map for Linux */
317 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
318
319 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
320 #if defined(CONFIG_CMD_KGDB)
321 #  define CONFIG_SYS_CACHELINE_SHIFT    5 /* log base 2 of the above value */
322 #endif
323
324 #define CONFIG_SYS_HID0_INIT            0
325 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
326
327 #define CONFIG_SYS_HID2         0
328
329 #define CONFIG_SYS_SIUMCR               0x4020c200
330 #define CONFIG_SYS_SYPCR                0xFFFFFF83
331 #define CONFIG_SYS_BCR                  0x10000000
332 #define CONFIG_SYS_SCCR         (SCCR_PCI_MODE | SCCR_PCI_MODCK)
333
334 /*
335  *-----------------------------------------------------------------------
336  * RMR - Reset Mode Register                                     5-5
337  *-----------------------------------------------------------------------
338  * turn on Checkstop Reset Enable
339  */
340 #define CONFIG_SYS_RMR         0
341
342 /*
343  *-----------------------------------------------------------------------
344  * TMCNTSC - Time Counter Status and Control                     4-40
345  *-----------------------------------------------------------------------
346  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
347  * and enable Time Counter
348  */
349 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
350
351 /*
352  *-----------------------------------------------------------------------
353  * PISCR - Periodic Interrupt Status and Control                 4-42
354  *-----------------------------------------------------------------------
355  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
356  * Periodic timer
357  */
358 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
359
360 /*
361  *-----------------------------------------------------------------------
362  * RCCR - RISC Controller Configuration                         13-7
363  *-----------------------------------------------------------------------
364  */
365 #define CONFIG_SYS_RCCR        0
366
367 /*
368  * Init Memory Controller:
369  *
370  * Bank Bus     Machine PortSz  Device
371  * ---- ---     ------- ------  ------
372  *  0   60x     GPCM     8 bit  FLASH
373  *  1   60x     SDRAM   32 bit  SDRAM
374  *  3   60x     GPCM     8 bit  GPIO/PIGGY
375  *  5   60x     GPCM    16 bit  CFG-Flash
376  *
377  */
378 /* Bank 0 - FLASH
379  */
380 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)    |\
381                          BRx_PS_8                       |\
382                          BRx_MS_GPCM_P                  |\
383                          BRx_V)
384
385 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)        |\
386                          ORxG_CSNT                      |\
387                          ORxG_ACS_DIV2                  |\
388                          ORxG_SCY_5_CLK                 |\
389                          ORxG_TRLX)
390
391 #define CONFIG_SYS_MPTPR       0x1800
392
393 /*
394  *-----------------------------------------------------------------------------
395  * Address for Mode Register Set (MRS) command
396  *-----------------------------------------------------------------------------
397  */
398 #define CONFIG_SYS_MRS_OFFS     0x00000110
399 #define CONFIG_SYS_PSRT        0x0e
400
401 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
402                          BRx_PS_64              |\
403                          BRx_MS_SDRAM_P         |\
404                          BRx_V)
405
406 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1
407
408 /*
409  * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
410  */
411 #define CONFIG_SYS_KMBEC_FPGA_BASE      0x30000000
412 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
413
414 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
415                          BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
416
417 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
418                          ORxG_CSNT | ORxG_ACS_DIV2 |\
419                          ORxG_SCY_3_CLK | ORxG_TRLX)
420
421 /*
422  * BFTICU board FPGA on CS4 initialization values
423  */
424 #define CONFIG_SYS_FPGA_BASE    0x40000000
425 #define CONFIG_SYS_FPGA_SIZE    1 /*1KB*/
426
427 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
428                         BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
429
430 #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
431                          ORxG_CSNT | ORxG_ACS_DIV2 |\
432                          ORxG_SCY_3_CLK | ORxG_TRLX)
433
434 /*
435  * CFG-Flash on CS5 initialization values
436  */
437 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
438                          BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
439
440 #define CONFIG_SYS_OR5_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
441                                  CONFIG_SYS_FLASH_SIZE_2) |\
442                                  ORxG_CSNT | ORxG_ACS_DIV2 |\
443                                  ORxG_SCY_5_CLK | ORxG_TRLX)
444
445 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC     /* "bad" address */
446
447 /* pass open firmware flat tree */
448 #define CONFIG_FIT              1
449 #define CONFIG_OF_LIBFDT        1
450 #define CONFIG_OF_BOARD_SETUP   1
451
452 #define OF_TBCLK                (bd->bi_busfreq / 4)
453 #define OF_STDOUT_PATH          "/soc/cpm/serial@11a90"
454
455 #endif /* __CONFIG_H */