include/configs/km82xx.h

   1 /*
   2  * (C) Copyright 2007-2011
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC8247
  33 /* MGCOGE */
  34 #if defined(CONFIG_MGCOGE)
  35 #define CONFIG_HOSTNAME         mgcoge
  36 #define CONFIG_KM_BOARD_EXTRA_ENV       ""
  37
  38 /* MGCOGE3NE */
  39 #elif defined(CONFIG_MGCOGE3NE)
  40 #define CONFIG_HOSTNAME         mgcoge3ne
  41 #define CONFIG_KM_82XX
  42 #define CONFIG_KM_BOARD_EXTRA_ENV       "bobcatreset=true\0"
  43
  44 #else
  45 #error ("Board unsupported")
  46 #endif
  47
  48 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  49
  50 /* include common defines/options for all Keymile boards */
  51 #include "km/keymile-common.h"
  52 #include "km/km-powerpc.h"
  53
  54 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  55 #define CONFIG_SYS_FLASH_BASE           0xFE000000
  56 #define CONFIG_SYS_FLASH_SIZE           32
  57 #define CONFIG_SYS_FLASH_CFI
  58 #define CONFIG_FLASH_CFI_DRIVER
  59
  60 /* MGCOGE */
  61 #if defined(CONFIG_MGCOGE)
  62 #define CONFIG_SYS_MAX_FLASH_BANKS      3
  63 /* max num of sects on one chip */
  64 #define CONFIG_SYS_MAX_FLASH_SECT       512
  65
  66 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
  67 #define CONFIG_SYS_FLASH_SIZE_1 32
  68 #define CONFIG_SYS_FLASH_BASE_2 0x52000000
  69 #define CONFIG_SYS_FLASH_SIZE_2 32
  70
  71 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
  72                                         CONFIG_SYS_FLASH_BASE_1, \
  73                                         CONFIG_SYS_FLASH_BASE_2 }
  74 #define MTDIDS_DEFAULT          "nor3=app"
  75
  76 /*
  77  * Bank 1 - 60x bus SDRAM
  78  */
  79 #define SDRAM_MAX_SIZE  0x08000000                      /* max. 128 MB  */
  80 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (256 << 20)     /* less than 256 MB */
  81
  82 /* SDRAM initialization values
  83 */
  84
  85 #define CONFIG_SYS_OR1  ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
  86                            ORxS_SDAM_MSK)               |\
  87                         ORxS_BPD_8                      |\
  88                         ORxS_ROWST_PBI0_A7              |\
  89                         ORxS_NUMR_13)
  90
  91 #define CONFIG_SYS_PSDMR (                              \
  92                         PSDMR_SDAM_A14_IS_A5            |\
  93                         PSDMR_BSMA_A14_A16              |\
  94                         PSDMR_SDA10_PBI0_A9             |\
  95                         PSDMR_RFRC_5_CLK                |\
  96                         PSDMR_PRETOACT_2W               |\
  97                         PSDMR_ACTTORW_2W                |\
  98                         PSDMR_LDOTOPRE_1C               |\
  99                         PSDMR_WRC_1C                    |\
 100                         PSDMR_CL_2)
 101
 102 /* MGCOGE3NE */
 103 #elif defined(CONFIG_MGCOGE3NE)
 104 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of flash banks */
 105 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /*
 106                                                  * max num of sects on one
 107                                                  * chip
 108                                                  */
 109
 110 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
 111 #define CONFIG_SYS_FLASH_SIZE_1 128
 112
 113 #define CONFIG_SYS_FLASH_SIZE_2 0       /* dummy value to calc SYS_OR5 */
 114
 115 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
 116                                         CONFIG_SYS_FLASH_BASE_1 }
 117
 118 #define MTDIDS_DEFAULT          "nor2=app"
 119
 120 /*
 121  * Bank 1 - 60x bus SDRAM
 122  * mgcoge3ne has 256MB
 123  * mgcoge2ne has 128MB
 124  */
 125 #define SDRAM_MAX_SIZE 0x10000000                       /* max. 256 MB  */
 126 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (512 << 20)     /* less than 512 MB */
 127
 128 #define CONFIG_SYS_OR1  ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
 129                            ORxS_SDAM_MSK)               |\
 130                         ORxS_BPD_4                      |\
 131                         ORxS_NUMR_13                    |\
 132                         ORxS_IBID)
 133
 134 #define CONFIG_SYS_PSDMR (                              \
 135                         PSDMR_PBI                       |\
 136                         PSDMR_RFEN                      |\
 137                         PSDMR_BSMA_A13_A15              |\
 138                         PSDMR_RFRC_5_CLK                |\
 139                         PSDMR_PRETOACT_2W               |\
 140                         PSDMR_ACTTORW_2W                |\
 141                         PSDMR_LDOTOPRE_1C               |\
 142                         PSDMR_WRC_1C                    |\
 143                         PSDMR_CL_2)
 144
 145 #define CONFIG_SYS_SDRAM_LIST   {                                       \
 146         {       .size   = 256 << 20,                                    \
 147                 .or1    = ORxS_ROWST_PBI1_A4,                           \
 148                 .psdmr  = PSDMR_SDAM_A17_IS_A5 | PSDMR_SDA10_PBI1_A6,   \
 149         },                                                              \
 150         {       .size   = 128 << 20,                                    \
 151                 .or1    = ORxS_ROWST_PBI1_A5,                           \
 152                 .psdmr  = PSDMR_SDAM_A16_IS_A5 | PSDMR_SDA10_PBI1_A7,   \
 153         },                                                              \
 154 }
 155 #endif /* defined(CONFIG_MGCOGE3NE) */
 156
 157 /* include further common stuff for all keymile 82xx boards */
 158 /*
 159  * Select serial console configuration
 160  *
 161  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 162  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 163  * for SCC).
 164  */
 165 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
 166 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
 167 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
 168 #define CONFIG_CONS_INDEX       2       /* SMC2 is used for console  */
 169 #define CONFIG_SYS_SMC_RXBUFLEN 128
 170 #define CONFIG_SYS_MAXIDLE      10
 171
 172 /*
 173  * Select ethernet configuration
 174  *
 175  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
 176  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
 177  * SCC, 1-3 for FCC)
 178  *
 179  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
 180  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
 181  * must be unset.
 182  */
 183 #define CONFIG_ETHER_ON_SCC             /* Ethernet is on SCC */
 184 #undef  CONFIG_ETHER_ON_FCC             /* Ethernet is not on FCC     */
 185 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
 186
 187 #define CONFIG_ETHER_INDEX      4
 188 #define CONFIG_HAS_ETH0
 189 #define CONFIG_SYS_SCC_TOUT_LOOP        10000000
 190
 191 #define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
 192
 193 #ifndef CONFIG_8260_CLKIN
 194 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 195 #endif
 196
 197 #define BOOTFLASH_START         0xFE000000
 198
 199 #define CONFIG_KM_CONSOLE_TTY   "ttyCPM0"
 200
 201 #define MTDPARTS_DEFAULT        "mtdparts="                             \
 202         "app:"                                                          \
 203                 "768k(u-boot),"                                         \
 204                 "128k(env),"                                            \
 205                 "128k(envred),"                                         \
 206                 "3072k(free),"                                          \
 207                 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")"
 208
 209 /*
 210  * Default environment settings
 211  */
 212 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 213         CONFIG_KM_BOARD_EXTRA_ENV                                       \
 214         CONFIG_KM_DEF_ENV                                               \
 215         "EEprom_ivm=pca9544a:70:4 \0"                                   \
 216         "unlock=yes\0"                                                  \
 217         "newenv="                                                       \
 218                 "prot off 0xFE0C0000 +0x40000 && "                      \
 219                 "era 0xFE0C0000 +0x40000\0"                             \
 220         "arch=ppc_82xx\0"                                       \
 221         ""
 222
 223 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 224 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 225 #define CONFIG_SYS_RAMBOOT
 226 #endif
 227
 228 #define CONFIG_SYS_MONITOR_LEN          (768 << 10)
 229
 230 #define CONFIG_ENV_IS_IN_FLASH
 231
 232 #ifdef CONFIG_ENV_IS_IN_FLASH
 233 #define CONFIG_ENV_SECT_SIZE    0x20000
 234 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 235                                         CONFIG_SYS_MONITOR_LEN)
 236 #define CONFIG_ENV_OFFSET       CONFIG_SYS_MONITOR_LEN
 237
 238 /* Address and size of Redundant Environment Sector     */
 239 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 240                                                 CONFIG_ENV_SECT_SIZE)
 241 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
 242 #endif /* CONFIG_ENV_IS_IN_FLASH */
 243
 244 /* enable I2C and select the hardware/software driver */
 245 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 246 #define CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 247 #define CONFIG_SYS_I2C_SPEED            50000   /* I2C speed */
 248 #define CONFIG_SYS_I2C_SLAVE            0x7F    /* I2C slave address */
 249
 250 /*
 251  * Software (bit-bang) I2C driver configuration
 252  */
 253
 254 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 255 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 256 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 257 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 258 #define I2C_SDA(bit)    do { \
 259                                 if (bit) \
 260                                         iop->pdat |=  0x00010000; \
 261                                 else \
 262                                         iop->pdat &= ~0x00010000; \
 263                         } while (0)
 264 #define I2C_SCL(bit)    do { \
 265                                 if (bit) \
 266                                         iop->pdat |=  0x00020000; \
 267                                 else \
 268                                         iop->pdat &= ~0x00020000; \
 269                         } while (0)
 270 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 271
 272 #ifndef __ASSEMBLY__
 273 void set_sda(int state);
 274 void set_scl(int state);
 275 int get_sda(void);
 276 int get_scl(void);
 277 #endif
 278
 279 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 280 #define CONFIG_DTT_LM75                 /* ON Semi's LM75               */
 281 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
 282 #define CONFIG_SYS_DTT_MAX_TEMP 70
 283 #define CONFIG_SYS_DTT_LOW_TEMP -30
 284 #define CONFIG_SYS_DTT_HYSTERESIS       3
 285 #define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
 286
 287 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 288
 289 #define CONFIG_SYS_IMMR         0xF0000000
 290
 291 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 292 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000 /* used size in DPRAM */
 293 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 294                                                 GENERATED_GBL_DATA_SIZE)
 295 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 296
 297 /* Hard reset configuration word */
 298 #define CONFIG_SYS_HRCW_MASTER          0x0604b211
 299
 300 /* No slaves */
 301 #define CONFIG_SYS_HRCW_SLAVE1          0
 302 #define CONFIG_SYS_HRCW_SLAVE2          0
 303 #define CONFIG_SYS_HRCW_SLAVE3          0
 304 #define CONFIG_SYS_HRCW_SLAVE4          0
 305 #define CONFIG_SYS_HRCW_SLAVE5          0
 306 #define CONFIG_SYS_HRCW_SLAVE6          0
 307 #define CONFIG_SYS_HRCW_SLAVE7          0
 308
 309 /* Initial Memory map for Linux */
 310 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 311
 312 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
 313 #if defined(CONFIG_CMD_KGDB)
 314 #  define CONFIG_SYS_CACHELINE_SHIFT    5 /* log base 2 of the above value */
 315 #endif
 316
 317 #define CONFIG_SYS_HID0_INIT            0
 318 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
 319
 320 #define CONFIG_SYS_HID2         0
 321
 322 #define CONFIG_SYS_SIUMCR               0x4020c200
 323 #define CONFIG_SYS_SYPCR                0xFFFFFF83
 324 #define CONFIG_SYS_BCR                  0x10000000
 325 #define CONFIG_SYS_SCCR         (SCCR_PCI_MODE | SCCR_PCI_MODCK)
 326
 327 /*
 328  *-----------------------------------------------------------------------
 329  * RMR - Reset Mode Register                                     5-5
 330  *-----------------------------------------------------------------------
 331  * turn on Checkstop Reset Enable
 332  */
 333 #define CONFIG_SYS_RMR         0
 334
 335 /*
 336  *-----------------------------------------------------------------------
 337  * TMCNTSC - Time Counter Status and Control                     4-40
 338  *-----------------------------------------------------------------------
 339  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 340  * and enable Time Counter
 341  */
 342 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 343
 344 /*
 345  *-----------------------------------------------------------------------
 346  * PISCR - Periodic Interrupt Status and Control                 4-42
 347  *-----------------------------------------------------------------------
 348  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 349  * Periodic timer
 350  */
 351 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 352
 353 /*
 354  *-----------------------------------------------------------------------
 355  * RCCR - RISC Controller Configuration                         13-7
 356  *-----------------------------------------------------------------------
 357  */
 358 #define CONFIG_SYS_RCCR        0
 359
 360 /*
 361  * Init Memory Controller:
 362  *
 363  * Bank Bus     Machine PortSz  Device
 364  * ---- ---     ------- ------  ------
 365  *  0   60x     GPCM     8 bit  FLASH
 366  *  1   60x     SDRAM   32 bit  SDRAM
 367  *  3   60x     GPCM     8 bit  GPIO/PIGGY
 368  *  5   60x     GPCM    16 bit  CFG-Flash
 369  *
 370  */
 371 /* Bank 0 - FLASH
 372  */
 373 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)    |\
 374                          BRx_PS_8                       |\
 375                          BRx_MS_GPCM_P                  |\
 376                          BRx_V)
 377
 378 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)        |\
 379                          ORxG_CSNT                      |\
 380                          ORxG_ACS_DIV2                  |\
 381                          ORxG_SCY_5_CLK                 |\
 382                          ORxG_TRLX)
 383
 384 #define CONFIG_SYS_MPTPR       0x1800
 385
 386 /*
 387  *-----------------------------------------------------------------------------
 388  * Address for Mode Register Set (MRS) command
 389  *-----------------------------------------------------------------------------
 390  */
 391 #define CONFIG_SYS_MRS_OFFS     0x00000110
 392 #define CONFIG_SYS_PSRT        0x0e
 393
 394 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
 395                          BRx_PS_64              |\
 396                          BRx_MS_SDRAM_P         |\
 397                          BRx_V)
 398
 399 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1
 400
 401 /*
 402  * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
 403  */
 404 #define CONFIG_SYS_KMBEC_FPGA_BASE      0x30000000
 405 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 406
 407 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
 408                          BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 409
 410 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
 411                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 412                          ORxG_SCY_3_CLK | ORxG_TRLX)
 413
 414 /*
 415  * BFTICU board FPGA on CS4 initialization values
 416  */
 417 #define CONFIG_SYS_FPGA_BASE    0x40000000
 418 #define CONFIG_SYS_FPGA_SIZE    1 /*1KB*/
 419
 420 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
 421                         BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 422
 423 #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
 424                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 425                          ORxG_SCY_3_CLK | ORxG_TRLX)
 426
 427 /*
 428  * CFG-Flash on CS5 initialization values
 429  */
 430 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
 431                          BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
 432
 433 #define CONFIG_SYS_OR5_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
 434                                  CONFIG_SYS_FLASH_SIZE_2) |\
 435                                  ORxG_CSNT | ORxG_ACS_DIV2 |\
 436                                  ORxG_SCY_5_CLK | ORxG_TRLX)
 437
 438 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC     /* "bad" address */
 439
 440 /* pass open firmware flat tree */
 441 #define CONFIG_FIT              1
 442 #define CONFIG_OF_LIBFDT        1
 443 #define CONFIG_OF_BOARD_SETUP   1
 444
 445 #define OF_TBCLK                (bd->bi_busfreq / 4)
 446 #define OF_STDOUT_PATH          "/soc/cpm/serial@11a90"
 447
 448 #endif /* __CONFIG_H */