1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2020 Hitachi Power Grids. All rights reserved.
6 #ifndef __CONFIG_PG_WCOM_LS102XA_H
7 #define __CONFIG_PG_WCOM_LS102XA_H
9 /* include common defines/options for all Keymile boards */
10 #include "keymile-common.h"
12 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
13 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
15 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \
17 CONFIG_KM_RESERVED_PRAM) >> 10)
19 #define CONFIG_SYS_CLK_FREQ 66666666
21 #define PHYS_SDRAM 0x80000000
22 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
24 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
25 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
27 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
28 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
30 #define CONFIG_SYS_SPD_BUS_NUM 0
31 #define SPD_EEPROM_ADDRESS 0x54
33 /* POST memory regions test */
34 #define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS)
35 #define CONFIG_POST_EXTERNAL_WORD_FUNCS
40 /* NOR Flash Definitions */
41 #define CONFIG_SYS_FLASH_BASE 0x60000000
42 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
44 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
45 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
50 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024)
52 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \
53 CSOR_NOR_ADM_SHIFT(0x4) | \
54 CSOR_NOR_NOR_MODE_ASYNC_NOR | \
57 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
58 FTIM0_NOR_TEADC(0x7) | \
59 FTIM0_NOR_TAVDS(0x0) | \
61 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
62 FTIM1_NOR_TRAD_NOR(0x21) | \
63 FTIM1_NOR_TSEQRAD_NOR(0x21))
64 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
65 FTIM2_NOR_TCH(0x1) | \
66 FTIM2_NOR_TWPH(0x6) | \
68 #define CONFIG_SYS_NOR_FTIM3 0
70 #define CONFIG_SYS_FLASH_QUIET_TEST
71 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
73 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
74 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
75 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
76 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
78 #define CONFIG_SYS_FLASH_EMPTY_INFO
79 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
81 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
82 #define CONFIG_SYS_WRITE_SWAPPED_DATA
84 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
85 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
86 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
87 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
88 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
89 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
90 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
91 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
93 /* NAND Flash Definitions */
94 #define CONFIG_SYS_NAND_BASE 0x68000000
95 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
97 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
98 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
103 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
104 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
105 | CSOR_NAND_ECC_DEC_EN \
106 | CSOR_NAND_ECC_MODE_4 \
109 | CSOR_NAND_SPRZ_64 \
111 | CSOR_NAND_TRHZ_40 \
114 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
115 FTIM0_NAND_TWP(0x8) | \
116 FTIM0_NAND_TWCHT(0x3) | \
118 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
119 FTIM1_NAND_TWBE(0x1e) | \
120 FTIM1_NAND_TRR(0x6) | \
122 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
123 FTIM2_NAND_TREH(0x5) | \
124 FTIM2_NAND_TWHRE(0x3c))
125 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
127 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
128 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
129 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
130 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
131 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
132 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
133 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
134 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
136 #define CONFIG_SYS_MAX_NAND_DEVICE 1
137 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
139 /* QRIO FPGA Definitions */
140 #define CONFIG_SYS_QRIO_BASE 0x70000000
141 #define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE
143 #define CONFIG_SYS_CSPR2_EXT (0x00)
144 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
149 #define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024)
150 #define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \
151 CSOR_GPCM_TRHZ_20 | \
153 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
154 FTIM0_GPCM_TEADC(0x8) | \
155 FTIM0_GPCM_TEAHC(0x2))
156 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
157 FTIM1_GPCM_TRAD(0x6))
158 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
159 FTIM2_GPCM_TCH(0x1) | \
161 #define CONFIG_SYS_CS2_FTIM3 0x04000000
166 #define CONFIG_SYS_NS16550_SERIAL
167 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
172 #define CONFIG_SYS_I2C_INIT_BOARD
174 #define CONFIG_I2C_MULTI_BUS
175 #define CONFIG_SYS_I2C_MAX_HOPS 1
176 #define CONFIG_SYS_NUM_I2C_BUSES 3
177 #define I2C_MUX_PCA_ADDR 0x70
178 #define I2C_MUX_CH_DEFAULT 0x0
179 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
180 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
181 {1, {I2C_NULL_HOP} }, \
187 #ifdef CONFIG_TSEC_ENET
188 #define CONFIG_ETHPRIME "ethernet@2d90000"
191 #define CONFIG_LAYERSCAPE_NS_ACCESS
192 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
193 #define COUNTER_FREQUENCY 8333333
195 #define CONFIG_HWCONFIG
196 #define HWCONFIG_BUFFER_SIZE 256
197 #define CONFIG_FSL_DEVICE_DISABLE
200 * Miscellaneous configurable options
203 #define CONFIG_LS102XA_STREAM_ID
205 #define CONFIG_SYS_INIT_SP_OFFSET \
206 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
207 #define CONFIG_SYS_INIT_SP_ADDR \
208 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
210 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
211 #define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */
213 #define CONFIG_SYS_BOOTCOUNT_BE
219 #define CONFIG_ENV_TOTAL_SIZE 0x40000
220 #define ENV_DEL_ADDR CONFIG_ENV_ADDR_REDUND /* direct for newenv */
222 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
223 #define CONFIG_KM_DEF_ENV
226 #ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU
227 #define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
230 #define CONFIG_KM_DEF_ENV_CPU \
231 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
233 "cramfsload ${fdt_addr_r} " \
234 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
235 "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
236 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
237 " +${filesize} && " \
238 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \
239 " +${filesize} && " \
240 "cp.b ${load_addr_r} " \
241 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
242 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
244 "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
245 " +${filesize} && " \
246 "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
247 " +${filesize} && " \
248 "cp.b ${load_addr_r} " \
249 __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
250 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
251 " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \
252 "set_fdthigh=true\0" \
256 #define CONFIG_KM_NEW_ENV \
257 "newenv=protect off " __stringify(ENV_DEL_ADDR) \
258 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
259 "erase " __stringify(ENV_DEL_ADDR) \
260 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
261 "protect on " __stringify(ENV_DEL_ADDR) \
262 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
264 #define CONFIG_HW_ENV_SETTINGS \
265 "hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi," \
266 "can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6," \
267 "asrc,spdif,lpuart1,ftm1\0"
269 #define CONFIG_EXTRA_ENV_SETTINGS \
272 CONFIG_HW_ENV_SETTINGS \
273 "EEprom_ivm=pca9547:70:9\0" \
277 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
278 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */