1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2020 Hitachi Power Grids. All rights reserved.
6 #ifndef __CONFIG_PG_WCOM_LS102XA_H
7 #define __CONFIG_PG_WCOM_LS102XA_H
9 /* include common defines/options for all Keymile boards */
10 #include "keymile-common.h"
12 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
13 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
15 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \
17 CONFIG_KM_RESERVED_PRAM) >> 10)
19 #define PHYS_SDRAM 0x80000000
20 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
22 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
23 #define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
25 #define SPD_EEPROM_ADDRESS 0x54
27 /* POST memory regions test */
28 #define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS)
29 #define CONFIG_POST_EXTERNAL_WORD_FUNCS
34 /* NOR Flash Definitions */
35 #define CONFIG_SYS_FLASH_BASE 0x60000000
36 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
38 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
39 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
44 #define CFG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024)
46 #define CFG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \
47 CSOR_NOR_ADM_SHIFT(0x4) | \
48 CSOR_NOR_NOR_MODE_ASYNC_NOR | \
51 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
52 FTIM0_NOR_TEADC(0x7) | \
53 FTIM0_NOR_TAVDS(0x0) | \
55 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
56 FTIM1_NOR_TRAD_NOR(0x21) | \
57 FTIM1_NOR_TSEQRAD_NOR(0x21))
58 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
59 FTIM2_NOR_TCH(0x1) | \
60 FTIM2_NOR_TWPH(0x6) | \
62 #define CFG_SYS_NOR_FTIM3 0
64 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
66 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
68 #define CONFIG_SYS_WRITE_SWAPPED_DATA
70 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
71 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
72 #define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
73 #define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
74 #define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
75 #define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
76 #define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
77 #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
79 /* NAND Flash Definitions */
80 #define CFG_SYS_NAND_BASE 0x68000000
81 #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
83 #define CFG_SYS_NAND_CSPR_EXT (0x0)
84 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \
89 #define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
90 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
91 | CSOR_NAND_ECC_DEC_EN \
92 | CSOR_NAND_ECC_MODE_4 \
100 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
101 FTIM0_NAND_TWP(0x8) | \
102 FTIM0_NAND_TWCHT(0x3) | \
104 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
105 FTIM1_NAND_TWBE(0x1e) | \
106 FTIM1_NAND_TRR(0x6) | \
108 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
109 FTIM2_NAND_TREH(0x5) | \
110 FTIM2_NAND_TWHRE(0x3c))
111 #define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
113 #define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
114 #define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
115 #define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
116 #define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
117 #define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
118 #define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
119 #define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
120 #define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
122 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
124 /* QRIO FPGA Definitions */
125 #define CONFIG_SYS_QRIO_BASE 0x70000000
126 #define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE
128 #define CONFIG_SYS_CSPR2_EXT (0x00)
129 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
134 #define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024)
135 #define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \
136 CSOR_GPCM_TRHZ_20 | \
138 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
139 FTIM0_GPCM_TEADC(0x8) | \
140 FTIM0_GPCM_TEAHC(0x2))
141 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
142 FTIM1_GPCM_TRAD(0x6))
143 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
144 FTIM2_GPCM_TCH(0x1) | \
146 #define CONFIG_SYS_CS2_FTIM3 0x04000000
151 #define CFG_SYS_NS16550_CLK get_serial_clock()
157 #define CONFIG_I2C_MULTI_BUS
158 #define CONFIG_SYS_I2C_MAX_HOPS 1
159 #define CFG_SYS_NUM_I2C_BUSES 3
160 #define I2C_MUX_PCA_ADDR 0x70
161 #define I2C_MUX_CH_DEFAULT 0x0
162 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
163 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
164 {1, {I2C_NULL_HOP} }, \
167 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
169 #define CONFIG_HWCONFIG
170 #define HWCONFIG_BUFFER_SIZE 256
171 #define CONFIG_FSL_DEVICE_DISABLE
174 * Miscellaneous configurable options
177 #define CONFIG_LS102XA_STREAM_ID
183 #define CONFIG_ENV_TOTAL_SIZE 0x40000
184 #define ENV_DEL_ADDR CONFIG_ENV_ADDR_REDUND /* direct for newenv */
186 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
187 #define CONFIG_KM_DEF_ENV
190 #ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU
191 #define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
194 #define CONFIG_KM_DEF_ENV_CPU \
195 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
197 "cramfsload ${fdt_addr_r} " \
198 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
199 "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
200 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
201 " +${filesize} && " \
202 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \
203 " +${filesize} && " \
204 "cp.b ${load_addr_r} " \
205 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
206 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
208 "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
209 " +${filesize} && " \
210 "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
211 " +${filesize} && " \
212 "cp.b ${load_addr_r} " \
213 __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
214 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
215 " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \
216 "set_fdthigh=true\0" \
220 #define CONFIG_KM_NEW_ENV \
221 "newenv=protect off " __stringify(ENV_DEL_ADDR) \
222 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
223 "erase " __stringify(ENV_DEL_ADDR) \
224 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
225 "protect on " __stringify(ENV_DEL_ADDR) \
226 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
228 #define CONFIG_HW_ENV_SETTINGS \
229 "hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi," \
230 "can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6," \
231 "asrc,spdif,lpuart1,ftm1\0"
233 #define CONFIG_EXTRA_ENV_SETTINGS \
236 CONFIG_HW_ENV_SETTINGS \
237 "EEprom_ivm=pca9547:70:9\0" \
241 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */