1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2020 Hitachi Power Grids. All rights reserved.
6 #ifndef __CONFIG_PG_WCOM_LS102XA_H
7 #define __CONFIG_PG_WCOM_LS102XA_H
9 /* include common defines/options for all Keymile boards */
10 #include "keymile-common.h"
12 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
13 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
15 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \
17 CONFIG_KM_RESERVED_PRAM) >> 10)
19 #define PHYS_SDRAM 0x80000000
20 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
22 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
23 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
25 #define CONFIG_SYS_SPD_BUS_NUM 0
26 #define SPD_EEPROM_ADDRESS 0x54
28 /* POST memory regions test */
29 #define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS)
30 #define CONFIG_POST_EXTERNAL_WORD_FUNCS
35 /* NOR Flash Definitions */
36 #define CONFIG_SYS_FLASH_BASE 0x60000000
37 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
39 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
40 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
45 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024)
47 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \
48 CSOR_NOR_ADM_SHIFT(0x4) | \
49 CSOR_NOR_NOR_MODE_ASYNC_NOR | \
52 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
53 FTIM0_NOR_TEADC(0x7) | \
54 FTIM0_NOR_TAVDS(0x0) | \
56 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
57 FTIM1_NOR_TRAD_NOR(0x21) | \
58 FTIM1_NOR_TSEQRAD_NOR(0x21))
59 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
60 FTIM2_NOR_TCH(0x1) | \
61 FTIM2_NOR_TWPH(0x6) | \
63 #define CONFIG_SYS_NOR_FTIM3 0
65 #define CONFIG_SYS_FLASH_QUIET_TEST
66 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
68 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
69 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
70 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
72 #define CONFIG_SYS_FLASH_EMPTY_INFO
73 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
75 #define CONFIG_SYS_WRITE_SWAPPED_DATA
77 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
78 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
79 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
80 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
81 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
82 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
83 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
84 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
86 /* NAND Flash Definitions */
87 #define CONFIG_SYS_NAND_BASE 0x68000000
88 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
90 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
91 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
96 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
97 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
98 | CSOR_NAND_ECC_DEC_EN \
99 | CSOR_NAND_ECC_MODE_4 \
102 | CSOR_NAND_SPRZ_64 \
104 | CSOR_NAND_TRHZ_40 \
107 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
108 FTIM0_NAND_TWP(0x8) | \
109 FTIM0_NAND_TWCHT(0x3) | \
111 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
112 FTIM1_NAND_TWBE(0x1e) | \
113 FTIM1_NAND_TRR(0x6) | \
115 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
116 FTIM2_NAND_TREH(0x5) | \
117 FTIM2_NAND_TWHRE(0x3c))
118 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
120 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
121 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
122 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
123 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
124 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
125 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
126 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
127 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
129 #define CONFIG_SYS_MAX_NAND_DEVICE 1
130 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
132 /* QRIO FPGA Definitions */
133 #define CONFIG_SYS_QRIO_BASE 0x70000000
134 #define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE
136 #define CONFIG_SYS_CSPR2_EXT (0x00)
137 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
142 #define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024)
143 #define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \
144 CSOR_GPCM_TRHZ_20 | \
146 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
147 FTIM0_GPCM_TEADC(0x8) | \
148 FTIM0_GPCM_TEAHC(0x2))
149 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
150 FTIM1_GPCM_TRAD(0x6))
151 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
152 FTIM2_GPCM_TCH(0x1) | \
154 #define CONFIG_SYS_CS2_FTIM3 0x04000000
159 #define CONFIG_SYS_NS16550_SERIAL
160 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
165 #define CONFIG_SYS_I2C_INIT_BOARD
167 #define CONFIG_I2C_MULTI_BUS
168 #define CONFIG_SYS_I2C_MAX_HOPS 1
169 #define CONFIG_SYS_NUM_I2C_BUSES 3
170 #define I2C_MUX_PCA_ADDR 0x70
171 #define I2C_MUX_CH_DEFAULT 0x0
172 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
173 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
174 {1, {I2C_NULL_HOP} }, \
177 #define CONFIG_LAYERSCAPE_NS_ACCESS
178 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
180 #define CONFIG_HWCONFIG
181 #define HWCONFIG_BUFFER_SIZE 256
182 #define CONFIG_FSL_DEVICE_DISABLE
185 * Miscellaneous configurable options
188 #define CONFIG_LS102XA_STREAM_ID
190 #define CONFIG_SYS_INIT_SP_OFFSET \
191 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
192 #define CONFIG_SYS_INIT_SP_ADDR \
193 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
195 #define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */
197 #define CONFIG_SYS_BOOTCOUNT_BE
203 #define CONFIG_ENV_TOTAL_SIZE 0x40000
204 #define ENV_DEL_ADDR CONFIG_ENV_ADDR_REDUND /* direct for newenv */
206 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
207 #define CONFIG_KM_DEF_ENV
210 #ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU
211 #define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
214 #define CONFIG_KM_DEF_ENV_CPU \
215 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
217 "cramfsload ${fdt_addr_r} " \
218 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
219 "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
220 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
221 " +${filesize} && " \
222 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \
223 " +${filesize} && " \
224 "cp.b ${load_addr_r} " \
225 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
226 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
228 "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
229 " +${filesize} && " \
230 "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
231 " +${filesize} && " \
232 "cp.b ${load_addr_r} " \
233 __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
234 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
235 " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \
236 "set_fdthigh=true\0" \
240 #define CONFIG_KM_NEW_ENV \
241 "newenv=protect off " __stringify(ENV_DEL_ADDR) \
242 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
243 "erase " __stringify(ENV_DEL_ADDR) \
244 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
245 "protect on " __stringify(ENV_DEL_ADDR) \
246 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
248 #define CONFIG_HW_ENV_SETTINGS \
249 "hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi," \
250 "can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6," \
251 "asrc,spdif,lpuart1,ftm1\0"
253 #define CONFIG_EXTRA_ENV_SETTINGS \
256 CONFIG_HW_ENV_SETTINGS \
257 "EEprom_ivm=pca9547:70:9\0" \
261 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
262 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */