include/configs/km/pg-wcom-ls102xa.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2020 Hitachi Power Grids. All rights reserved.
   4  */
   5
   6 #ifndef __CONFIG_PG_WCOM_LS102XA_H
   7 #define __CONFIG_PG_WCOM_LS102XA_H
   8
   9 #define CONFIG_SYS_FSL_CLK
  10
  11 #define CONFIG_SKIP_LOWLEVEL_INIT
  12
  13 /* include common defines/options for all Keymile boards */
  14 #include "keymile-common.h"
  15
  16 /*
  17  * Size of malloc() pool
  18  */
  19 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  20
  21 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  22 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  23
  24 #define CONFIG_SYS_CLK_FREQ             66666666
  25 /*
  26  * Take into account default implementation where DDR_FDBK_MULTI is consider as
  27  * configured for DDR_PLL = 2*MEM_PLL_RAT.
  28  * In our case DDR_FDBK_MULTI is 2, means DDR_PLL = MEM_PLL_RAT.
  29  */
  30 #define CONFIG_DDR_CLK_FREQ             (100000000 >> 1)
  31
  32 #define PHYS_SDRAM                      0x80000000
  33 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  34
  35 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  36 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  37
  38 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  39 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  40
  41 #define CONFIG_DDR_SPD
  42
  43 #define CONFIG_SYS_SPD_BUS_NUM          0
  44 #define SPD_EEPROM_ADDRESS              0x54
  45
  46 /* POST memory regions test */
  47 #define CONFIG_POST                     (CONFIG_SYS_POST_MEM_REGIONS)
  48 #define CONFIG_POST_EXTERNAL_WORD_FUNCS
  49
  50 /*
  51  * IFC Definitions
  52  */
  53 /* NOR Flash Definitions */
  54 #define CONFIG_FSL_IFC
  55 #define CONFIG_SYS_FLASH_BASE           0x60000000
  56 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  57
  58 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  59 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  60                                 CSPR_PORT_SIZE_16 | \
  61                                 CSPR_TE | \
  62                                 CSPR_MSEL_NOR | \
  63                                 CSPR_V)
  64 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(64 * 1024 * 1024)
  65
  66 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_AVD_TGL_PGM_EN | \
  67                                         CSOR_NOR_ADM_SHIFT(0x4) | \
  68                                         CSOR_NOR_NOR_MODE_ASYNC_NOR | \
  69                                         CSOR_NOR_TRHZ_20 | \
  70                                         CSOR_NOR_BCTLD)
  71 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x1) | \
  72                                         FTIM0_NOR_TEADC(0x7) | \
  73                                         FTIM0_NOR_TAVDS(0x0) | \
  74                                         FTIM0_NOR_TEAHC(0x1))
  75 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x1) | \
  76                                         FTIM1_NOR_TRAD_NOR(0x21) | \
  77                                         FTIM1_NOR_TSEQRAD_NOR(0x21))
  78 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x1) | \
  79                                         FTIM2_NOR_TCH(0x1) | \
  80                                         FTIM2_NOR_TWPH(0x6) | \
  81                                         FTIM2_NOR_TWP(0xb))
  82 #define CONFIG_SYS_NOR_FTIM3            0
  83
  84 #define CONFIG_SYS_FLASH_QUIET_TEST
  85 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
  86
  87 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  88 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
  89 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  90 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  91
  92 #define CONFIG_SYS_FLASH_EMPTY_INFO
  93 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  94
  95 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  96 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  97
  98 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
  99 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 100 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 101 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 102 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 103 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 104 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 105 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 106
 107 /* NAND Flash Definitions */
 108 #define CONFIG_NAND_FSL_IFC
 109 #define CONFIG_SYS_NAND_BASE            0x68000000
 110 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 111
 112 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 113 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
 114                                 CSPR_PORT_SIZE_8 | \
 115                                 CSPR_TE | \
 116                                 CSPR_MSEL_NAND | \
 117                                 CSPR_V)
 118 #define CONFIG_SYS_NAND_AMASK           IFC_AMASK(64 * 1024)
 119 #define CONFIG_SYS_NAND_CSOR            (CSOR_NAND_ECC_ENC_EN \
 120                                         | CSOR_NAND_ECC_DEC_EN \
 121                                         | CSOR_NAND_ECC_MODE_4 \
 122                                         | CSOR_NAND_RAL_3 \
 123                                         | CSOR_NAND_PGS_2K \
 124                                         | CSOR_NAND_SPRZ_64 \
 125                                         | CSOR_NAND_PB(64) \
 126                                         | CSOR_NAND_TRHZ_40 \
 127                                         | CSOR_NAND_BCTLD)
 128
 129 #define CONFIG_SYS_NAND_ONFI_DETECTION
 130
 131 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x3) | \
 132                                         FTIM0_NAND_TWP(0x8) | \
 133                                         FTIM0_NAND_TWCHT(0x3) | \
 134                                         FTIM0_NAND_TWH(0x5))
 135 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x1e) | \
 136                                         FTIM1_NAND_TWBE(0x1e) | \
 137                                         FTIM1_NAND_TRR(0x6) | \
 138                                         FTIM1_NAND_TRP(0x8))
 139 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x9) | \
 140                                         FTIM2_NAND_TREH(0x5) | \
 141                                         FTIM2_NAND_TWHRE(0x3c))
 142 #define CONFIG_SYS_NAND_FTIM3           (FTIM3_NAND_TWW(0x1e))
 143
 144 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 145 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 146 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 147 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 148 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 149 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 150 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 151 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 152
 153 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 154 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 155 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 156
 157 /* QRIO FPGA Definitions */
 158 #define CONFIG_SYS_QRIO_BASE            0x70000000
 159 #define CONFIG_SYS_QRIO_BASE_PHYS       CONFIG_SYS_QRIO_BASE
 160
 161 #define CONFIG_SYS_CSPR2_EXT            (0x00)
 162 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
 163                                         CSPR_PORT_SIZE_8 | \
 164                                         CSPR_TE | \
 165                                         CSPR_MSEL_GPCM | \
 166                                         CSPR_V)
 167 #define CONFIG_SYS_AMASK2               IFC_AMASK(64 * 1024)
 168 #define CONFIG_SYS_CSOR2                (CSOR_GPCM_ADM_SHIFT(0x4) | \
 169                                         CSOR_GPCM_TRHZ_20 | \
 170                                         CSOR_GPCM_BCTLD)
 171 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x2) | \
 172                                         FTIM0_GPCM_TEADC(0x8) | \
 173                                         FTIM0_GPCM_TEAHC(0x2))
 174 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x2) | \
 175                                         FTIM1_GPCM_TRAD(0x6))
 176 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x1) | \
 177                                         FTIM2_GPCM_TCH(0x1) | \
 178                                         FTIM2_GPCM_TWP(0x7))
 179 #define CONFIG_SYS_CS2_FTIM3            0x04000000
 180
 181 /*
 182  * Serial Port
 183  */
 184 #define CONFIG_SYS_NS16550_SERIAL
 185 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 186
 187 /*
 188  * I2C
 189  */
 190 #define CONFIG_SYS_I2C
 191 #define CONFIG_SYS_I2C_INIT_BOARD
 192 #define CONFIG_SYS_I2C_SPEED            100000
 193
 194 #define CONFIG_I2C_MULTI_BUS
 195 #define CONFIG_SYS_I2C_MAX_HOPS         1
 196 #define CONFIG_SYS_NUM_I2C_BUSES        3
 197 #define I2C_MUX_PCA_ADDR                0x70
 198 #define I2C_MUX_CH_DEFAULT              0x0
 199 #define CONFIG_SYS_I2C_BUSES    {       {0, {I2C_NULL_HOP} }, \
 200                                         {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
 201                                         {1, {I2C_NULL_HOP}                 }, \
 202                                 }
 203
 204 /*
 205  * eTSEC
 206  */
 207 #ifdef CONFIG_TSEC_ENET
 208 #define CONFIG_ETHPRIME                 "ethernet@2d90000"
 209 #endif
 210
 211 #define CONFIG_LAYERSCAPE_NS_ACCESS
 212 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 213 #define COUNTER_FREQUENCY               12500000
 214
 215 #define CONFIG_HWCONFIG
 216 #define HWCONFIG_BUFFER_SIZE            256
 217 #define CONFIG_FSL_DEVICE_DISABLE
 218
 219 /*
 220  * Miscellaneous configurable options
 221  */
 222
 223 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 224
 225 #define CONFIG_LS102XA_STREAM_ID
 226
 227 #define CONFIG_SYS_INIT_SP_OFFSET \
 228         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 229 #define CONFIG_SYS_INIT_SP_ADDR \
 230         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 231
 232 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 233 #define CONFIG_SYS_MONITOR_LEN          0x100000     /* 1Mbyte */
 234 #define CONFIG_SYS_QE_FW_ADDR           0x60020000
 235
 236 #define CONFIG_SYS_BOOTCOUNT_BE
 237
 238 /*
 239  * Environment
 240  */
 241
 242 #define CONFIG_ENV_TOTAL_SIZE           0x40000
 243 #define ENV_DEL_ADDR            CONFIG_ENV_ADDR_REDUND  /* direct for newenv */
 244
 245 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 246 #define CONFIG_KM_DEF_ENV
 247 #endif
 248
 249 #ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU
 250 #define CONFIG_KM_DEF_BOOT_ARGS_CPU             ""
 251 #endif
 252
 253 #define CONFIG_KM_DEF_ENV_CPU                                           \
 254         "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"                   \
 255         "cramfsloadfdt="                                                \
 256                 "cramfsload ${fdt_addr_r} "                             \
 257                 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"             \
 258         "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"                       \
 259         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 260                 " +${filesize} && "                                     \
 261                 "erase " __stringify(CONFIG_SYS_MONITOR_BASE)           \
 262                 " +${filesize} && "                                     \
 263                 "cp.b ${load_addr_r} "                                  \
 264                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
 265                 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 266                 " +${filesize}\0"                                       \
 267         "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE)    \
 268                 " +${filesize} && "                                     \
 269                 "erase " __stringify(CONFIG_SYS_FLASH_BASE)             \
 270                 " +${filesize} && "                                     \
 271                 "cp.b ${load_addr_r} "                                  \
 272                 __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && "   \
 273                 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 274                 " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0"            \
 275         "set_fdthigh=true\0"                    \
 276         "checkfdt=true\0"                                               \
 277         ""
 278
 279 #define CONFIG_KM_NEW_ENV                                               \
 280         "newenv=protect off " __stringify(ENV_DEL_ADDR)                 \
 281                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "          \
 282                 "erase " __stringify(ENV_DEL_ADDR)                      \
 283                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "          \
 284                 "protect on " __stringify(ENV_DEL_ADDR)                 \
 285                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
 286
 287 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 288         CONFIG_KM_NEW_ENV                                               \
 289         CONFIG_KM_DEF_ENV                                               \
 290         "EEprom_ivm=pca9547:70:9\0"                                     \
 291         ""
 292
 293 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 294 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Increase map for Linux */
 295
 296 #endif