include/configs/km/pg-wcom-ls102xa.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2020 Hitachi Power Grids. All rights reserved.
   4  */
   5
   6 #ifndef __CONFIG_PG_WCOM_LS102XA_H
   7 #define __CONFIG_PG_WCOM_LS102XA_H
   8
   9 /* include common defines/options for all Keymile boards */
  10 #include "keymile-common.h"
  11
  12 #define CFG_SYS_INIT_RAM_ADDR   OCRAM_BASE_ADDR
  13 #define CFG_SYS_INIT_RAM_SIZE   OCRAM_SIZE
  14
  15 #define CONFIG_PRAM                     ((CONFIG_KM_PNVRAM + \
  16                                           CONFIG_KM_PHRAM + \
  17                                           CONFIG_KM_RESERVED_PRAM) >> 10)
  18
  19 #define PHYS_SDRAM                      0x80000000
  20 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  21
  22 #define CFG_SYS_DDR_SDRAM_BASE  0x80000000UL
  23 #define CFG_SYS_SDRAM_BASE              CFG_SYS_DDR_SDRAM_BASE
  24
  25 #define SPD_EEPROM_ADDRESS              0x54
  26
  27 /* POST memory regions test */
  28 #define CONFIG_POST                     (CFG_SYS_POST_MEM_REGIONS)
  29 #define CONFIG_POST_EXTERNAL_WORD_FUNCS
  30
  31 /*
  32  * IFC Definitions
  33  */
  34 /* NOR Flash Definitions */
  35 #define CFG_SYS_FLASH_BASE              0x60000000
  36 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
  37
  38 #define CFG_SYS_NOR0_CSPR_EXT   (0x0)
  39 #define CFG_SYS_NOR0_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
  40                                 CSPR_PORT_SIZE_16 | \
  41                                 CSPR_TE | \
  42                                 CSPR_MSEL_NOR | \
  43                                 CSPR_V)
  44 #define CFG_SYS_NOR_AMASK               IFC_AMASK(64 * 1024 * 1024)
  45
  46 #define CFG_SYS_NOR_CSOR                (CSOR_NOR_AVD_TGL_PGM_EN | \
  47                                         CSOR_NOR_ADM_SHIFT(0x4) | \
  48                                         CSOR_NOR_NOR_MODE_ASYNC_NOR | \
  49                                         CSOR_NOR_TRHZ_20 | \
  50                                         CSOR_NOR_BCTLD)
  51 #define CFG_SYS_NOR_FTIM0               (FTIM0_NOR_TACSE(0x1) | \
  52                                         FTIM0_NOR_TEADC(0x7) | \
  53                                         FTIM0_NOR_TAVDS(0x0) | \
  54                                         FTIM0_NOR_TEAHC(0x1))
  55 #define CFG_SYS_NOR_FTIM1               (FTIM1_NOR_TACO(0x1) | \
  56                                         FTIM1_NOR_TRAD_NOR(0x21) | \
  57                                         FTIM1_NOR_TSEQRAD_NOR(0x21))
  58 #define CFG_SYS_NOR_FTIM2               (FTIM2_NOR_TCS(0x1) | \
  59                                         FTIM2_NOR_TCH(0x1) | \
  60                                         FTIM2_NOR_TWPH(0x6) | \
  61                                         FTIM2_NOR_TWP(0xb))
  62 #define CFG_SYS_NOR_FTIM3               0
  63
  64 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
  65
  66 #define CFG_SYS_FLASH_BANKS_LIST        { CFG_SYS_FLASH_BASE_PHYS }
  67
  68 #define CFG_SYS_WRITE_SWAPPED_DATA
  69
  70 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
  71 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR
  72 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
  73 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
  74 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
  75 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
  76 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
  77 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
  78
  79 /* NAND Flash Definitions */
  80 #define CFG_SYS_NAND_BASE               0x68000000
  81 #define CFG_SYS_NAND_BASE_PHYS  CFG_SYS_NAND_BASE
  82
  83 #define CFG_SYS_NAND_CSPR_EXT   (0x0)
  84 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \
  85                                 CSPR_PORT_SIZE_8 | \
  86                                 CSPR_TE | \
  87                                 CSPR_MSEL_NAND | \
  88                                 CSPR_V)
  89 #define CFG_SYS_NAND_AMASK              IFC_AMASK(64 * 1024)
  90 #define CFG_SYS_NAND_CSOR               (CSOR_NAND_ECC_ENC_EN \
  91                                         | CSOR_NAND_ECC_DEC_EN \
  92                                         | CSOR_NAND_ECC_MODE_4 \
  93                                         | CSOR_NAND_RAL_3 \
  94                                         | CSOR_NAND_PGS_2K \
  95                                         | CSOR_NAND_SPRZ_64 \
  96                                         | CSOR_NAND_PB(64) \
  97                                         | CSOR_NAND_TRHZ_40 \
  98                                         | CSOR_NAND_BCTLD)
  99
 100 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x3) | \
 101                                         FTIM0_NAND_TWP(0x8) | \
 102                                         FTIM0_NAND_TWCHT(0x3) | \
 103                                         FTIM0_NAND_TWH(0x5))
 104 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x1e) | \
 105                                         FTIM1_NAND_TWBE(0x1e) | \
 106                                         FTIM1_NAND_TRR(0x6) | \
 107                                         FTIM1_NAND_TRP(0x8))
 108 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0x9) | \
 109                                         FTIM2_NAND_TREH(0x5) | \
 110                                         FTIM2_NAND_TWHRE(0x3c))
 111 #define CFG_SYS_NAND_FTIM3              (FTIM3_NAND_TWW(0x1e))
 112
 113 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NAND_CSPR_EXT
 114 #define CFG_SYS_CSPR1           CFG_SYS_NAND_CSPR
 115 #define CFG_SYS_AMASK1          CFG_SYS_NAND_AMASK
 116 #define CFG_SYS_CSOR1           CFG_SYS_NAND_CSOR
 117 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NAND_FTIM0
 118 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NAND_FTIM1
 119 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NAND_FTIM2
 120 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NAND_FTIM3
 121
 122 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 123
 124 /* QRIO FPGA Definitions */
 125 #define CFG_SYS_QRIO_BASE               0x70000000
 126 #define CFG_SYS_QRIO_BASE_PHYS  CFG_SYS_QRIO_BASE
 127
 128 #define CFG_SYS_CSPR2_EXT               (0x00)
 129 #define CFG_SYS_CSPR2   (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \
 130                                         CSPR_PORT_SIZE_8 | \
 131                                         CSPR_TE | \
 132                                         CSPR_MSEL_GPCM | \
 133                                         CSPR_V)
 134 #define CFG_SYS_AMASK2          IFC_AMASK(64 * 1024)
 135 #define CFG_SYS_CSOR2           (CSOR_GPCM_ADM_SHIFT(0x4) | \
 136                                         CSOR_GPCM_TRHZ_20 | \
 137                                         CSOR_GPCM_BCTLD)
 138 #define CFG_SYS_CS2_FTIM0               (FTIM0_GPCM_TACSE(0x2) | \
 139                                         FTIM0_GPCM_TEADC(0x8) | \
 140                                         FTIM0_GPCM_TEAHC(0x2))
 141 #define CFG_SYS_CS2_FTIM1               (FTIM1_GPCM_TACO(0x2) | \
 142                                         FTIM1_GPCM_TRAD(0x6))
 143 #define CFG_SYS_CS2_FTIM2               (FTIM2_GPCM_TCS(0x1) | \
 144                                         FTIM2_GPCM_TCH(0x1) | \
 145                                         FTIM2_GPCM_TWP(0x7))
 146 #define CFG_SYS_CS2_FTIM3               0x04000000
 147
 148 /*
 149  * Serial Port
 150  */
 151 #define CFG_SYS_NS16550_CLK             get_serial_clock()
 152
 153 /*
 154  * I2C
 155  */
 156
 157 #define CONFIG_I2C_MULTI_BUS
 158 #define CFG_SYS_I2C_MAX_HOPS            1
 159 #define CFG_SYS_NUM_I2C_BUSES   3
 160 #define I2C_MUX_PCA_ADDR                0x70
 161 #define I2C_MUX_CH_DEFAULT              0x0
 162 #define CFG_SYS_I2C_BUSES       {       {0, {I2C_NULL_HOP} }, \
 163                                         {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
 164                                         {1, {I2C_NULL_HOP}                 }, \
 165                                 }
 166
 167 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 168
 169 #define CONFIG_HWCONFIG
 170 #define HWCONFIG_BUFFER_SIZE            256
 171
 172 /*
 173  * Miscellaneous configurable options
 174  */
 175
 176 #define CONFIG_LS102XA_STREAM_ID
 177
 178 /*
 179  * Environment
 180  */
 181
 182 #define CONFIG_ENV_TOTAL_SIZE           0x40000
 183 #define ENV_DEL_ADDR            CONFIG_ENV_ADDR_REDUND  /* direct for newenv */
 184
 185 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 186 #define CONFIG_KM_DEF_ENV
 187 #endif
 188
 189 #ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU
 190 #define CONFIG_KM_DEF_BOOT_ARGS_CPU             ""
 191 #endif
 192
 193 #define CONFIG_KM_DEF_ENV_CPU                                           \
 194         "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"                   \
 195         "cramfsloadfdt="                                                \
 196                 "cramfsload ${fdt_addr_r} "                             \
 197                 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"             \
 198         "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"                       \
 199         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 200                 " +${filesize} && "                                     \
 201                 "erase " __stringify(CONFIG_SYS_MONITOR_BASE)           \
 202                 " +${filesize} && "                                     \
 203                 "cp.b ${load_addr_r} "                                  \
 204                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
 205                 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 206                 " +${filesize}\0"                                       \
 207         "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE)       \
 208                 " +${filesize} && "                                     \
 209                 "erase " __stringify(CFG_SYS_FLASH_BASE)                \
 210                 " +${filesize} && "                                     \
 211                 "cp.b ${load_addr_r} "                                  \
 212                 __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && "      \
 213                 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 214                 " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0"            \
 215         "set_fdthigh=true\0"                    \
 216         "checkfdt=true\0"                                               \
 217         ""
 218
 219 #define CONFIG_KM_NEW_ENV                                               \
 220         "newenv=protect off " __stringify(ENV_DEL_ADDR)                 \
 221                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "          \
 222                 "erase " __stringify(ENV_DEL_ADDR)                      \
 223                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "          \
 224                 "protect on " __stringify(ENV_DEL_ADDR)                 \
 225                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
 226
 227 #define CONFIG_HW_ENV_SETTINGS                                          \
 228         "hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi,"     \
 229                         "can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6,"   \
 230                         "asrc,spdif,lpuart1,ftm1\0"
 231
 232 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 233         CONFIG_KM_NEW_ENV                                               \
 234         CONFIG_KM_DEF_ENV                                               \
 235         CONFIG_HW_ENV_SETTINGS                                          \
 236         "EEprom_ivm=pca9547:70:9\0"                                     \
 237         "ethrotate=no\0"                                                \
 238         ""
 239
 240 #define CFG_SYS_BOOTMAPSZ       (256 << 20) /* Increase map for Linux */
 241
 242 #endif