include/configs/km/pg-wcom-ls102xa.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2020 Hitachi Power Grids. All rights reserved.
   4  */
   5
   6 #ifndef __CONFIG_PG_WCOM_LS102XA_H
   7 #define __CONFIG_PG_WCOM_LS102XA_H
   8
   9 /* include common defines/options for all Keymile boards */
  10 #include "keymile-common.h"
  11
  12 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  13 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  14
  15 #define CONFIG_PRAM                     ((CONFIG_KM_PNVRAM + \
  16                                           CONFIG_KM_PHRAM + \
  17                                           CONFIG_KM_RESERVED_PRAM) >> 10)
  18
  19 #define PHYS_SDRAM                      0x80000000
  20 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  21
  22 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  23 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  24
  25 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  26 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  27
  28 #define CONFIG_SYS_SPD_BUS_NUM          0
  29 #define SPD_EEPROM_ADDRESS              0x54
  30
  31 /* POST memory regions test */
  32 #define CONFIG_POST                     (CONFIG_SYS_POST_MEM_REGIONS)
  33 #define CONFIG_POST_EXTERNAL_WORD_FUNCS
  34
  35 /*
  36  * IFC Definitions
  37  */
  38 /* NOR Flash Definitions */
  39 #define CONFIG_SYS_FLASH_BASE           0x60000000
  40 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  41
  42 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  43 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  44                                 CSPR_PORT_SIZE_16 | \
  45                                 CSPR_TE | \
  46                                 CSPR_MSEL_NOR | \
  47                                 CSPR_V)
  48 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(64 * 1024 * 1024)
  49
  50 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_AVD_TGL_PGM_EN | \
  51                                         CSOR_NOR_ADM_SHIFT(0x4) | \
  52                                         CSOR_NOR_NOR_MODE_ASYNC_NOR | \
  53                                         CSOR_NOR_TRHZ_20 | \
  54                                         CSOR_NOR_BCTLD)
  55 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x1) | \
  56                                         FTIM0_NOR_TEADC(0x7) | \
  57                                         FTIM0_NOR_TAVDS(0x0) | \
  58                                         FTIM0_NOR_TEAHC(0x1))
  59 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x1) | \
  60                                         FTIM1_NOR_TRAD_NOR(0x21) | \
  61                                         FTIM1_NOR_TSEQRAD_NOR(0x21))
  62 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x1) | \
  63                                         FTIM2_NOR_TCH(0x1) | \
  64                                         FTIM2_NOR_TWPH(0x6) | \
  65                                         FTIM2_NOR_TWP(0xb))
  66 #define CONFIG_SYS_NOR_FTIM3            0
  67
  68 #define CONFIG_SYS_FLASH_QUIET_TEST
  69 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
  70
  71 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
  72 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  73 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  74
  75 #define CONFIG_SYS_FLASH_EMPTY_INFO
  76 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  77
  78 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  79 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  80
  81 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
  82 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
  83 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
  84 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
  85 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
  86 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
  87 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
  88 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
  89
  90 /* NAND Flash Definitions */
  91 #define CONFIG_SYS_NAND_BASE            0x68000000
  92 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  93
  94 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  95 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
  96                                 CSPR_PORT_SIZE_8 | \
  97                                 CSPR_TE | \
  98                                 CSPR_MSEL_NAND | \
  99                                 CSPR_V)
 100 #define CONFIG_SYS_NAND_AMASK           IFC_AMASK(64 * 1024)
 101 #define CONFIG_SYS_NAND_CSOR            (CSOR_NAND_ECC_ENC_EN \
 102                                         | CSOR_NAND_ECC_DEC_EN \
 103                                         | CSOR_NAND_ECC_MODE_4 \
 104                                         | CSOR_NAND_RAL_3 \
 105                                         | CSOR_NAND_PGS_2K \
 106                                         | CSOR_NAND_SPRZ_64 \
 107                                         | CSOR_NAND_PB(64) \
 108                                         | CSOR_NAND_TRHZ_40 \
 109                                         | CSOR_NAND_BCTLD)
 110
 111 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x3) | \
 112                                         FTIM0_NAND_TWP(0x8) | \
 113                                         FTIM0_NAND_TWCHT(0x3) | \
 114                                         FTIM0_NAND_TWH(0x5))
 115 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x1e) | \
 116                                         FTIM1_NAND_TWBE(0x1e) | \
 117                                         FTIM1_NAND_TRR(0x6) | \
 118                                         FTIM1_NAND_TRP(0x8))
 119 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x9) | \
 120                                         FTIM2_NAND_TREH(0x5) | \
 121                                         FTIM2_NAND_TWHRE(0x3c))
 122 #define CONFIG_SYS_NAND_FTIM3           (FTIM3_NAND_TWW(0x1e))
 123
 124 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 125 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 126 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 127 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 128 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 129 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 130 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 131 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 132
 133 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 134 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 135
 136 /* QRIO FPGA Definitions */
 137 #define CONFIG_SYS_QRIO_BASE            0x70000000
 138 #define CONFIG_SYS_QRIO_BASE_PHYS       CONFIG_SYS_QRIO_BASE
 139
 140 #define CONFIG_SYS_CSPR2_EXT            (0x00)
 141 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
 142                                         CSPR_PORT_SIZE_8 | \
 143                                         CSPR_TE | \
 144                                         CSPR_MSEL_GPCM | \
 145                                         CSPR_V)
 146 #define CONFIG_SYS_AMASK2               IFC_AMASK(64 * 1024)
 147 #define CONFIG_SYS_CSOR2                (CSOR_GPCM_ADM_SHIFT(0x4) | \
 148                                         CSOR_GPCM_TRHZ_20 | \
 149                                         CSOR_GPCM_BCTLD)
 150 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x2) | \
 151                                         FTIM0_GPCM_TEADC(0x8) | \
 152                                         FTIM0_GPCM_TEAHC(0x2))
 153 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x2) | \
 154                                         FTIM1_GPCM_TRAD(0x6))
 155 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x1) | \
 156                                         FTIM2_GPCM_TCH(0x1) | \
 157                                         FTIM2_GPCM_TWP(0x7))
 158 #define CONFIG_SYS_CS2_FTIM3            0x04000000
 159
 160 /*
 161  * Serial Port
 162  */
 163 #define CONFIG_SYS_NS16550_SERIAL
 164 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 165
 166 /*
 167  * I2C
 168  */
 169 #define CONFIG_SYS_I2C_INIT_BOARD
 170
 171 #define CONFIG_I2C_MULTI_BUS
 172 #define CONFIG_SYS_I2C_MAX_HOPS         1
 173 #define CONFIG_SYS_NUM_I2C_BUSES        3
 174 #define I2C_MUX_PCA_ADDR                0x70
 175 #define I2C_MUX_CH_DEFAULT              0x0
 176 #define CONFIG_SYS_I2C_BUSES    {       {0, {I2C_NULL_HOP} }, \
 177                                         {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
 178                                         {1, {I2C_NULL_HOP}                 }, \
 179                                 }
 180
 181 /*
 182  * eTSEC
 183  */
 184 #ifdef CONFIG_TSEC_ENET
 185 #define CONFIG_ETHPRIME                 "ethernet@2d90000"
 186 #endif
 187
 188 #define CONFIG_LAYERSCAPE_NS_ACCESS
 189 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 190 #define COUNTER_FREQUENCY               8333333
 191
 192 #define CONFIG_HWCONFIG
 193 #define HWCONFIG_BUFFER_SIZE            256
 194 #define CONFIG_FSL_DEVICE_DISABLE
 195
 196 /*
 197  * Miscellaneous configurable options
 198  */
 199
 200 #define CONFIG_LS102XA_STREAM_ID
 201
 202 #define CONFIG_SYS_INIT_SP_OFFSET \
 203         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 204 #define CONFIG_SYS_INIT_SP_ADDR \
 205         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 206
 207 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 208 #define CONFIG_SYS_MONITOR_LEN          0x100000     /* 1Mbyte */
 209
 210 #define CONFIG_SYS_BOOTCOUNT_BE
 211
 212 /*
 213  * Environment
 214  */
 215
 216 #define CONFIG_ENV_TOTAL_SIZE           0x40000
 217 #define ENV_DEL_ADDR            CONFIG_ENV_ADDR_REDUND  /* direct for newenv */
 218
 219 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 220 #define CONFIG_KM_DEF_ENV
 221 #endif
 222
 223 #ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU
 224 #define CONFIG_KM_DEF_BOOT_ARGS_CPU             ""
 225 #endif
 226
 227 #define CONFIG_KM_DEF_ENV_CPU                                           \
 228         "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"                   \
 229         "cramfsloadfdt="                                                \
 230                 "cramfsload ${fdt_addr_r} "                             \
 231                 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"             \
 232         "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"                       \
 233         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 234                 " +${filesize} && "                                     \
 235                 "erase " __stringify(CONFIG_SYS_MONITOR_BASE)           \
 236                 " +${filesize} && "                                     \
 237                 "cp.b ${load_addr_r} "                                  \
 238                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
 239                 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 240                 " +${filesize}\0"                                       \
 241         "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE)    \
 242                 " +${filesize} && "                                     \
 243                 "erase " __stringify(CONFIG_SYS_FLASH_BASE)             \
 244                 " +${filesize} && "                                     \
 245                 "cp.b ${load_addr_r} "                                  \
 246                 __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && "   \
 247                 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 248                 " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0"            \
 249         "set_fdthigh=true\0"                    \
 250         "checkfdt=true\0"                                               \
 251         ""
 252
 253 #define CONFIG_KM_NEW_ENV                                               \
 254         "newenv=protect off " __stringify(ENV_DEL_ADDR)                 \
 255                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "          \
 256                 "erase " __stringify(ENV_DEL_ADDR)                      \
 257                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "          \
 258                 "protect on " __stringify(ENV_DEL_ADDR)                 \
 259                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
 260
 261 #define CONFIG_HW_ENV_SETTINGS                                          \
 262         "hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi,"     \
 263                         "can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6,"   \
 264                         "asrc,spdif,lpuart1,ftm1\0"
 265
 266 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 267         CONFIG_KM_NEW_ENV                                               \
 268         CONFIG_KM_DEF_ENV                                               \
 269         CONFIG_HW_ENV_SETTINGS                                          \
 270         "EEprom_ivm=pca9547:70:9\0"                                     \
 271         "ethrotate=no\0"                                                \
 272         ""
 273
 274 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 275 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Increase map for Linux */
 276
 277 #endif