1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2020 Hitachi Power Grids. All rights reserved.
6 #ifndef __CONFIG_PG_WCOM_LS102XA_H
7 #define __CONFIG_PG_WCOM_LS102XA_H
9 #define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
10 #define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
12 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \
14 CONFIG_KM_RESERVED_PRAM) >> 10)
16 #define PHYS_SDRAM 0x80000000
17 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
19 #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
20 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
22 #define SPD_EEPROM_ADDRESS 0x54
24 /* POST memory regions test */
25 #define CFG_POST (CFG_SYS_POST_MEM_REGIONS)
26 #define CFG_POST_EXTERNAL_WORD_FUNCS
31 /* NOR Flash Definitions */
32 #define CFG_SYS_FLASH_BASE 0x60000000
33 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
35 #define CFG_SYS_NOR0_CSPR_EXT (0x0)
36 #define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
41 #define CFG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024)
43 #define CFG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \
44 CSOR_NOR_ADM_SHIFT(0x4) | \
45 CSOR_NOR_NOR_MODE_ASYNC_NOR | \
48 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
49 FTIM0_NOR_TEADC(0x7) | \
50 FTIM0_NOR_TAVDS(0x0) | \
52 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
53 FTIM1_NOR_TRAD_NOR(0x21) | \
54 FTIM1_NOR_TSEQRAD_NOR(0x21))
55 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
56 FTIM2_NOR_TCH(0x1) | \
57 FTIM2_NOR_TWPH(0x6) | \
59 #define CFG_SYS_NOR_FTIM3 0
61 #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS }
63 #define CFG_SYS_WRITE_SWAPPED_DATA
65 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
66 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
67 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
68 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
69 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
70 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
71 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
72 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
74 /* NAND Flash Definitions */
75 #define CFG_SYS_NAND_BASE 0x68000000
76 #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
78 #define CFG_SYS_NAND_CSPR_EXT (0x0)
79 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \
84 #define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
85 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
86 | CSOR_NAND_ECC_DEC_EN \
87 | CSOR_NAND_ECC_MODE_4 \
95 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
96 FTIM0_NAND_TWP(0x8) | \
97 FTIM0_NAND_TWCHT(0x3) | \
99 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
100 FTIM1_NAND_TWBE(0x1e) | \
101 FTIM1_NAND_TRR(0x6) | \
103 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
104 FTIM2_NAND_TREH(0x5) | \
105 FTIM2_NAND_TWHRE(0x3c))
106 #define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
108 #define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
109 #define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
110 #define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
111 #define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
112 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
113 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
114 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
115 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
117 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
119 /* QRIO FPGA Definitions */
120 #define CFG_SYS_QRIO_BASE 0x70000000
121 #define CFG_SYS_QRIO_BASE_PHYS CFG_SYS_QRIO_BASE
123 #define CFG_SYS_CSPR2_EXT (0x00)
124 #define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \
129 #define CFG_SYS_AMASK2 IFC_AMASK(64 * 1024)
130 #define CFG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \
131 CSOR_GPCM_TRHZ_20 | \
133 #define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
134 FTIM0_GPCM_TEADC(0x8) | \
135 FTIM0_GPCM_TEAHC(0x2))
136 #define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
137 FTIM1_GPCM_TRAD(0x6))
138 #define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
139 FTIM2_GPCM_TCH(0x1) | \
141 #define CFG_SYS_CS2_FTIM3 0x04000000
146 #define CFG_SYS_NS16550_CLK get_serial_clock()
152 #define CFG_SYS_I2C_MAX_HOPS 1
153 #define CFG_SYS_NUM_I2C_BUSES 3
154 #define I2C_MUX_PCA_ADDR 0x70
155 #define I2C_MUX_CH_DEFAULT 0x0
156 #define CFG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
157 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
158 {1, {I2C_NULL_HOP} }, \
161 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
163 #define HWCONFIG_BUFFER_SIZE 256
165 #define CFG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */