include/configs/km/pg-wcom-ls102xa.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2020 Hitachi Power Grids. All rights reserved.
   4  */
   5
   6 #ifndef __CONFIG_PG_WCOM_LS102XA_H
   7 #define __CONFIG_PG_WCOM_LS102XA_H
   8
   9 #define CONFIG_SYS_FSL_CLK
  10
  11 #define CONFIG_SKIP_LOWLEVEL_INIT
  12
  13 /* include common defines/options for all Keymile boards */
  14 #include "keymile-common.h"
  15
  16 /*
  17  * Size of malloc() pool
  18  */
  19 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  20
  21 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  22 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  23
  24 #define CONFIG_PRAM                     ((CONFIG_KM_PNVRAM + \
  25                                           CONFIG_KM_PHRAM + \
  26                                           CONFIG_KM_RESERVED_PRAM) >> 10)
  27
  28 #define CONFIG_SYS_CLK_FREQ             66666666
  29 /*
  30  * Take into account default implementation where DDR_FDBK_MULTI is consider as
  31  * configured for DDR_PLL = 2*MEM_PLL_RAT.
  32  * In our case DDR_FDBK_MULTI is 2, means DDR_PLL = MEM_PLL_RAT.
  33  */
  34 #define CONFIG_DDR_CLK_FREQ             (100000000 >> 1)
  35
  36 #define PHYS_SDRAM                      0x80000000
  37 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  38
  39 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  40 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  41
  42 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  43 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  44
  45 #define CONFIG_DDR_SPD
  46
  47 #define CONFIG_SYS_SPD_BUS_NUM          0
  48 #define SPD_EEPROM_ADDRESS              0x54
  49
  50 /* POST memory regions test */
  51 #define CONFIG_POST                     (CONFIG_SYS_POST_MEM_REGIONS)
  52 #define CONFIG_POST_EXTERNAL_WORD_FUNCS
  53
  54 /*
  55  * IFC Definitions
  56  */
  57 /* NOR Flash Definitions */
  58 #define CONFIG_FSL_IFC
  59 #define CONFIG_SYS_FLASH_BASE           0x60000000
  60 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  61
  62 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  63 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  64                                 CSPR_PORT_SIZE_16 | \
  65                                 CSPR_TE | \
  66                                 CSPR_MSEL_NOR | \
  67                                 CSPR_V)
  68 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(64 * 1024 * 1024)
  69
  70 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_AVD_TGL_PGM_EN | \
  71                                         CSOR_NOR_ADM_SHIFT(0x4) | \
  72                                         CSOR_NOR_NOR_MODE_ASYNC_NOR | \
  73                                         CSOR_NOR_TRHZ_20 | \
  74                                         CSOR_NOR_BCTLD)
  75 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x1) | \
  76                                         FTIM0_NOR_TEADC(0x7) | \
  77                                         FTIM0_NOR_TAVDS(0x0) | \
  78                                         FTIM0_NOR_TEAHC(0x1))
  79 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x1) | \
  80                                         FTIM1_NOR_TRAD_NOR(0x21) | \
  81                                         FTIM1_NOR_TSEQRAD_NOR(0x21))
  82 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x1) | \
  83                                         FTIM2_NOR_TCH(0x1) | \
  84                                         FTIM2_NOR_TWPH(0x6) | \
  85                                         FTIM2_NOR_TWP(0xb))
  86 #define CONFIG_SYS_NOR_FTIM3            0
  87
  88 #define CONFIG_SYS_FLASH_QUIET_TEST
  89 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
  90
  91 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  92 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
  93 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  94 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  95
  96 #define CONFIG_SYS_FLASH_EMPTY_INFO
  97 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  98
  99 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 100 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 101
 102 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 103 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 104 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 105 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 106 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 107 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 108 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 109 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 110
 111 /* NAND Flash Definitions */
 112 #define CONFIG_NAND_FSL_IFC
 113 #define CONFIG_SYS_NAND_BASE            0x68000000
 114 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 115
 116 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 117 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
 118                                 CSPR_PORT_SIZE_8 | \
 119                                 CSPR_TE | \
 120                                 CSPR_MSEL_NAND | \
 121                                 CSPR_V)
 122 #define CONFIG_SYS_NAND_AMASK           IFC_AMASK(64 * 1024)
 123 #define CONFIG_SYS_NAND_CSOR            (CSOR_NAND_ECC_ENC_EN \
 124                                         | CSOR_NAND_ECC_DEC_EN \
 125                                         | CSOR_NAND_ECC_MODE_4 \
 126                                         | CSOR_NAND_RAL_3 \
 127                                         | CSOR_NAND_PGS_2K \
 128                                         | CSOR_NAND_SPRZ_64 \
 129                                         | CSOR_NAND_PB(64) \
 130                                         | CSOR_NAND_TRHZ_40 \
 131                                         | CSOR_NAND_BCTLD)
 132
 133 #define CONFIG_SYS_NAND_ONFI_DETECTION
 134
 135 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x3) | \
 136                                         FTIM0_NAND_TWP(0x8) | \
 137                                         FTIM0_NAND_TWCHT(0x3) | \
 138                                         FTIM0_NAND_TWH(0x5))
 139 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x1e) | \
 140                                         FTIM1_NAND_TWBE(0x1e) | \
 141                                         FTIM1_NAND_TRR(0x6) | \
 142                                         FTIM1_NAND_TRP(0x8))
 143 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x9) | \
 144                                         FTIM2_NAND_TREH(0x5) | \
 145                                         FTIM2_NAND_TWHRE(0x3c))
 146 #define CONFIG_SYS_NAND_FTIM3           (FTIM3_NAND_TWW(0x1e))
 147
 148 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 149 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 150 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 151 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 152 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 153 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 154 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 155 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 156
 157 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 158 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 159 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 160
 161 /* QRIO FPGA Definitions */
 162 #define CONFIG_SYS_QRIO_BASE            0x70000000
 163 #define CONFIG_SYS_QRIO_BASE_PHYS       CONFIG_SYS_QRIO_BASE
 164
 165 #define CONFIG_SYS_CSPR2_EXT            (0x00)
 166 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
 167                                         CSPR_PORT_SIZE_8 | \
 168                                         CSPR_TE | \
 169                                         CSPR_MSEL_GPCM | \
 170                                         CSPR_V)
 171 #define CONFIG_SYS_AMASK2               IFC_AMASK(64 * 1024)
 172 #define CONFIG_SYS_CSOR2                (CSOR_GPCM_ADM_SHIFT(0x4) | \
 173                                         CSOR_GPCM_TRHZ_20 | \
 174                                         CSOR_GPCM_BCTLD)
 175 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x2) | \
 176                                         FTIM0_GPCM_TEADC(0x8) | \
 177                                         FTIM0_GPCM_TEAHC(0x2))
 178 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x2) | \
 179                                         FTIM1_GPCM_TRAD(0x6))
 180 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x1) | \
 181                                         FTIM2_GPCM_TCH(0x1) | \
 182                                         FTIM2_GPCM_TWP(0x7))
 183 #define CONFIG_SYS_CS2_FTIM3            0x04000000
 184
 185 /*
 186  * Serial Port
 187  */
 188 #define CONFIG_SYS_NS16550_SERIAL
 189 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 190
 191 /*
 192  * I2C
 193  */
 194 #define CONFIG_SYS_I2C_LEGACY
 195 #define CONFIG_SYS_I2C_INIT_BOARD
 196 #define CONFIG_SYS_I2C_SPEED            100000
 197
 198 #define CONFIG_I2C_MULTI_BUS
 199 #define CONFIG_SYS_I2C_MAX_HOPS         1
 200 #define CONFIG_SYS_NUM_I2C_BUSES        3
 201 #define I2C_MUX_PCA_ADDR                0x70
 202 #define I2C_MUX_CH_DEFAULT              0x0
 203 #define CONFIG_SYS_I2C_BUSES    {       {0, {I2C_NULL_HOP} }, \
 204                                         {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
 205                                         {1, {I2C_NULL_HOP}                 }, \
 206                                 }
 207
 208 /*
 209  * eTSEC
 210  */
 211 #ifdef CONFIG_TSEC_ENET
 212 #define CONFIG_ETHPRIME                 "ethernet@2d90000"
 213 #endif
 214
 215 #define CONFIG_LAYERSCAPE_NS_ACCESS
 216 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 217 #define COUNTER_FREQUENCY               8333333
 218
 219 #define CONFIG_HWCONFIG
 220 #define HWCONFIG_BUFFER_SIZE            256
 221 #define CONFIG_FSL_DEVICE_DISABLE
 222
 223 /*
 224  * Miscellaneous configurable options
 225  */
 226
 227 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 228
 229 #define CONFIG_LS102XA_STREAM_ID
 230
 231 #define CONFIG_SYS_INIT_SP_OFFSET \
 232         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 233 #define CONFIG_SYS_INIT_SP_ADDR \
 234         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 235
 236 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 237 #define CONFIG_SYS_MONITOR_LEN          0x100000     /* 1Mbyte */
 238 #define CONFIG_SYS_QE_FW_ADDR           0x60020000
 239
 240 #define CONFIG_SYS_BOOTCOUNT_BE
 241
 242 /*
 243  * Environment
 244  */
 245
 246 #define CONFIG_ENV_TOTAL_SIZE           0x40000
 247 #define ENV_DEL_ADDR            CONFIG_ENV_ADDR_REDUND  /* direct for newenv */
 248
 249 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 250 #define CONFIG_KM_DEF_ENV
 251 #endif
 252
 253 #ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU
 254 #define CONFIG_KM_DEF_BOOT_ARGS_CPU             ""
 255 #endif
 256
 257 #define CONFIG_KM_DEF_ENV_CPU                                           \
 258         "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"                   \
 259         "cramfsloadfdt="                                                \
 260                 "cramfsload ${fdt_addr_r} "                             \
 261                 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"             \
 262         "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"                       \
 263         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 264                 " +${filesize} && "                                     \
 265                 "erase " __stringify(CONFIG_SYS_MONITOR_BASE)           \
 266                 " +${filesize} && "                                     \
 267                 "cp.b ${load_addr_r} "                                  \
 268                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
 269                 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 270                 " +${filesize}\0"                                       \
 271         "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE)    \
 272                 " +${filesize} && "                                     \
 273                 "erase " __stringify(CONFIG_SYS_FLASH_BASE)             \
 274                 " +${filesize} && "                                     \
 275                 "cp.b ${load_addr_r} "                                  \
 276                 __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && "   \
 277                 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 278                 " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0"            \
 279         "set_fdthigh=true\0"                    \
 280         "checkfdt=true\0"                                               \
 281         ""
 282
 283 #define CONFIG_KM_NEW_ENV                                               \
 284         "newenv=protect off " __stringify(ENV_DEL_ADDR)                 \
 285                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "          \
 286                 "erase " __stringify(ENV_DEL_ADDR)                      \
 287                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "          \
 288                 "protect on " __stringify(ENV_DEL_ADDR)                 \
 289                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
 290
 291 #define CONFIG_HW_ENV_SETTINGS                                          \
 292         "hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi,"     \
 293                         "can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6,"   \
 294                         "asrc,spdif,lpuart1,ftm1\0"
 295
 296 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 297         CONFIG_KM_NEW_ENV                                               \
 298         CONFIG_KM_DEF_ENV                                               \
 299         CONFIG_HW_ENV_SETTINGS                                          \
 300         "EEprom_ivm=pca9547:70:9\0"                                     \
 301         "ethrotate=no\0"                                                \
 302         ""
 303
 304 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 305 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Increase map for Linux */
 306
 307 #endif