include/configs/km/pg-wcom-ls102xa.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2020 Hitachi Power Grids. All rights reserved.
   4  */
   5
   6 #ifndef __CONFIG_PG_WCOM_LS102XA_H
   7 #define __CONFIG_PG_WCOM_LS102XA_H
   8
   9 /* include common defines/options for all Keymile boards */
  10 #include "keymile-common.h"
  11
  12 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  13 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  14
  15 #define CONFIG_PRAM                     ((CONFIG_KM_PNVRAM + \
  16                                           CONFIG_KM_PHRAM + \
  17                                           CONFIG_KM_RESERVED_PRAM) >> 10)
  18
  19 #define PHYS_SDRAM                      0x80000000
  20 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  21
  22 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  23 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  24
  25 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  26
  27 #define CONFIG_SYS_SPD_BUS_NUM          0
  28 #define SPD_EEPROM_ADDRESS              0x54
  29
  30 /* POST memory regions test */
  31 #define CONFIG_POST                     (CONFIG_SYS_POST_MEM_REGIONS)
  32 #define CONFIG_POST_EXTERNAL_WORD_FUNCS
  33
  34 /*
  35  * IFC Definitions
  36  */
  37 /* NOR Flash Definitions */
  38 #define CONFIG_SYS_FLASH_BASE           0x60000000
  39 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  40
  41 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  42 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  43                                 CSPR_PORT_SIZE_16 | \
  44                                 CSPR_TE | \
  45                                 CSPR_MSEL_NOR | \
  46                                 CSPR_V)
  47 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(64 * 1024 * 1024)
  48
  49 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_AVD_TGL_PGM_EN | \
  50                                         CSOR_NOR_ADM_SHIFT(0x4) | \
  51                                         CSOR_NOR_NOR_MODE_ASYNC_NOR | \
  52                                         CSOR_NOR_TRHZ_20 | \
  53                                         CSOR_NOR_BCTLD)
  54 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x1) | \
  55                                         FTIM0_NOR_TEADC(0x7) | \
  56                                         FTIM0_NOR_TAVDS(0x0) | \
  57                                         FTIM0_NOR_TEAHC(0x1))
  58 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x1) | \
  59                                         FTIM1_NOR_TRAD_NOR(0x21) | \
  60                                         FTIM1_NOR_TSEQRAD_NOR(0x21))
  61 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x1) | \
  62                                         FTIM2_NOR_TCH(0x1) | \
  63                                         FTIM2_NOR_TWPH(0x6) | \
  64                                         FTIM2_NOR_TWP(0xb))
  65 #define CONFIG_SYS_NOR_FTIM3            0
  66
  67 #define CONFIG_SYS_FLASH_QUIET_TEST
  68 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
  69
  70 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
  71 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  72 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  73
  74 #define CONFIG_SYS_FLASH_EMPTY_INFO
  75 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  76
  77 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  78
  79 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
  80 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
  81 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
  82 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
  83 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
  84 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
  85 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
  86 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
  87
  88 /* NAND Flash Definitions */
  89 #define CONFIG_SYS_NAND_BASE            0x68000000
  90 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  91
  92 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  93 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
  94                                 CSPR_PORT_SIZE_8 | \
  95                                 CSPR_TE | \
  96                                 CSPR_MSEL_NAND | \
  97                                 CSPR_V)
  98 #define CONFIG_SYS_NAND_AMASK           IFC_AMASK(64 * 1024)
  99 #define CONFIG_SYS_NAND_CSOR            (CSOR_NAND_ECC_ENC_EN \
 100                                         | CSOR_NAND_ECC_DEC_EN \
 101                                         | CSOR_NAND_ECC_MODE_4 \
 102                                         | CSOR_NAND_RAL_3 \
 103                                         | CSOR_NAND_PGS_2K \
 104                                         | CSOR_NAND_SPRZ_64 \
 105                                         | CSOR_NAND_PB(64) \
 106                                         | CSOR_NAND_TRHZ_40 \
 107                                         | CSOR_NAND_BCTLD)
 108
 109 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x3) | \
 110                                         FTIM0_NAND_TWP(0x8) | \
 111                                         FTIM0_NAND_TWCHT(0x3) | \
 112                                         FTIM0_NAND_TWH(0x5))
 113 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x1e) | \
 114                                         FTIM1_NAND_TWBE(0x1e) | \
 115                                         FTIM1_NAND_TRR(0x6) | \
 116                                         FTIM1_NAND_TRP(0x8))
 117 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x9) | \
 118                                         FTIM2_NAND_TREH(0x5) | \
 119                                         FTIM2_NAND_TWHRE(0x3c))
 120 #define CONFIG_SYS_NAND_FTIM3           (FTIM3_NAND_TWW(0x1e))
 121
 122 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 123 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 124 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 125 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 126 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 127 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 128 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 129 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 130
 131 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 132 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 133
 134 /* QRIO FPGA Definitions */
 135 #define CONFIG_SYS_QRIO_BASE            0x70000000
 136 #define CONFIG_SYS_QRIO_BASE_PHYS       CONFIG_SYS_QRIO_BASE
 137
 138 #define CONFIG_SYS_CSPR2_EXT            (0x00)
 139 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
 140                                         CSPR_PORT_SIZE_8 | \
 141                                         CSPR_TE | \
 142                                         CSPR_MSEL_GPCM | \
 143                                         CSPR_V)
 144 #define CONFIG_SYS_AMASK2               IFC_AMASK(64 * 1024)
 145 #define CONFIG_SYS_CSOR2                (CSOR_GPCM_ADM_SHIFT(0x4) | \
 146                                         CSOR_GPCM_TRHZ_20 | \
 147                                         CSOR_GPCM_BCTLD)
 148 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x2) | \
 149                                         FTIM0_GPCM_TEADC(0x8) | \
 150                                         FTIM0_GPCM_TEAHC(0x2))
 151 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x2) | \
 152                                         FTIM1_GPCM_TRAD(0x6))
 153 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x1) | \
 154                                         FTIM2_GPCM_TCH(0x1) | \
 155                                         FTIM2_GPCM_TWP(0x7))
 156 #define CONFIG_SYS_CS2_FTIM3            0x04000000
 157
 158 /*
 159  * Serial Port
 160  */
 161 #define CONFIG_SYS_NS16550_SERIAL
 162 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 163
 164 /*
 165  * I2C
 166  */
 167 #define CONFIG_SYS_I2C_INIT_BOARD
 168
 169 #define CONFIG_I2C_MULTI_BUS
 170 #define CONFIG_SYS_I2C_MAX_HOPS         1
 171 #define CONFIG_SYS_NUM_I2C_BUSES        3
 172 #define I2C_MUX_PCA_ADDR                0x70
 173 #define I2C_MUX_CH_DEFAULT              0x0
 174 #define CONFIG_SYS_I2C_BUSES    {       {0, {I2C_NULL_HOP} }, \
 175                                         {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
 176                                         {1, {I2C_NULL_HOP}                 }, \
 177                                 }
 178
 179 #define CONFIG_LAYERSCAPE_NS_ACCESS
 180 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 181 #define COUNTER_FREQUENCY               8333333
 182
 183 #define CONFIG_HWCONFIG
 184 #define HWCONFIG_BUFFER_SIZE            256
 185 #define CONFIG_FSL_DEVICE_DISABLE
 186
 187 /*
 188  * Miscellaneous configurable options
 189  */
 190
 191 #define CONFIG_LS102XA_STREAM_ID
 192
 193 #define CONFIG_SYS_INIT_SP_OFFSET \
 194         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 195 #define CONFIG_SYS_INIT_SP_ADDR \
 196         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 197
 198 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 199 #define CONFIG_SYS_MONITOR_LEN          0x100000     /* 1Mbyte */
 200
 201 #define CONFIG_SYS_BOOTCOUNT_BE
 202
 203 /*
 204  * Environment
 205  */
 206
 207 #define CONFIG_ENV_TOTAL_SIZE           0x40000
 208 #define ENV_DEL_ADDR            CONFIG_ENV_ADDR_REDUND  /* direct for newenv */
 209
 210 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 211 #define CONFIG_KM_DEF_ENV
 212 #endif
 213
 214 #ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU
 215 #define CONFIG_KM_DEF_BOOT_ARGS_CPU             ""
 216 #endif
 217
 218 #define CONFIG_KM_DEF_ENV_CPU                                           \
 219         "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"                   \
 220         "cramfsloadfdt="                                                \
 221                 "cramfsload ${fdt_addr_r} "                             \
 222                 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"             \
 223         "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"                       \
 224         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 225                 " +${filesize} && "                                     \
 226                 "erase " __stringify(CONFIG_SYS_MONITOR_BASE)           \
 227                 " +${filesize} && "                                     \
 228                 "cp.b ${load_addr_r} "                                  \
 229                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
 230                 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 231                 " +${filesize}\0"                                       \
 232         "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE)    \
 233                 " +${filesize} && "                                     \
 234                 "erase " __stringify(CONFIG_SYS_FLASH_BASE)             \
 235                 " +${filesize} && "                                     \
 236                 "cp.b ${load_addr_r} "                                  \
 237                 __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && "   \
 238                 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 239                 " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0"            \
 240         "set_fdthigh=true\0"                    \
 241         "checkfdt=true\0"                                               \
 242         ""
 243
 244 #define CONFIG_KM_NEW_ENV                                               \
 245         "newenv=protect off " __stringify(ENV_DEL_ADDR)                 \
 246                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "          \
 247                 "erase " __stringify(ENV_DEL_ADDR)                      \
 248                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "          \
 249                 "protect on " __stringify(ENV_DEL_ADDR)                 \
 250                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
 251
 252 #define CONFIG_HW_ENV_SETTINGS                                          \
 253         "hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi,"     \
 254                         "can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6,"   \
 255                         "asrc,spdif,lpuart1,ftm1\0"
 256
 257 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 258         CONFIG_KM_NEW_ENV                                               \
 259         CONFIG_KM_DEF_ENV                                               \
 260         CONFIG_HW_ENV_SETTINGS                                          \
 261         "EEprom_ivm=pca9547:70:9\0"                                     \
 262         "ethrotate=no\0"                                                \
 263         ""
 264
 265 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 266 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Increase map for Linux */
 267
 268 #endif