3 * Marvell Semiconductor <www.marvell.com>
4 * Prafulla Wadaskar <prafulla@marvell.com>
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * (C) Copyright 2010-2011
10 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
12 * SPDX-License-Identifier: GPL-2.0+
16 * for linking errors see
17 * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
20 #ifndef _CONFIG_KM_ARM_H
21 #define _CONFIG_KM_ARM_H
24 * High Level Configuration Options (easy to change)
26 #define CONFIG_MARVELL
27 #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
28 #define CONFIG_KW88F6281 /* SOC Name */
29 #define CONFIG_MACH_KM_KIRKWOOD /* Machine type */
31 #define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD
33 #define CONFIG_NAND_ECC_BCH
36 /* include common defines/options for all Keymile boards */
37 #include "keymile-common.h"
39 #define CONFIG_CMD_NAND
41 /* SPI NOR Flash default params, used by sf commands */
42 #define CONFIG_SF_DEFAULT_SPEED 8100000
43 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
45 #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
46 #define CONFIG_ENV_SPI_BUS 0
47 #define CONFIG_ENV_SPI_CS 0
48 #define CONFIG_ENV_SPI_MAX_HZ 8100000
49 #define CONFIG_ENV_SPI_MODE SPI_MODE_3
52 /* Reserve 4 MB for malloc */
53 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
55 #include "asm/arch/config.h"
57 #define CONFIG_SYS_TEXT_BASE 0x07d00000 /* code address before reloc */
58 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
59 #define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
60 #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
62 /* pseudo-non volatile RAM [hex] */
63 #define CONFIG_KM_PNVRAM 0x80000
64 /* physical RAM MTD size [hex] */
65 #define CONFIG_KM_PHRAM 0x17F000
67 #define CONFIG_KM_CRAMFS_ADDR 0x2400000
68 #define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 3098KBytes */
69 #define CONFIG_KM_FDT_ADDR 0x23E0000 /* 128KBytes */
71 /* architecture specific default bootargs */
72 #define CONFIG_KM_DEF_BOOT_ARGS_CPU \
73 "bootcountaddr=${bootcountaddr} ${mtdparts}" \
74 " boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"
76 #define CONFIG_KM_DEF_ENV_CPU \
77 "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0" \
78 CONFIG_KM_UPDATE_UBOOT \
79 "set_fdthigh=setenv fdt_high ${kernelmem}\0" \
81 "if cramfsls fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; " \
82 "then true; else setenv cramfsloadfdt true; " \
83 "setenv boot bootm ${load_addr_r}; " \
84 "echo No FDT found, booting with the kernel " \
85 "appended one; fi\0" \
88 #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
89 #define CONFIG_MISC_INIT_R
92 * NS16550 Configuration
94 #define CONFIG_SYS_NS16550_SERIAL
95 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
96 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
97 #define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
98 #define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE
101 * Serial Port configuration
102 * The following definitions let you select what serial you want to use
103 * for your console driver.
106 #define CONFIG_CONS_INDEX 1 /* Console on UART0 */
109 * For booting Linux, the board info and command line data
110 * have to be in the first 8 MB of memory, since this is
111 * the maximum mapped by the Linux kernel during initialization.
113 #define CONFIG_BOOTMAPSZ (8 << 20) /* Initial Memmap for Linux */
114 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
115 #define CONFIG_INITRD_TAG /* enable INITRD tag */
116 #define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
119 * Commands configuration
121 #define CONFIG_CMD_MTDPARTS
124 * Without NOR FLASH we need this
126 #define CONFIG_SYS_NO_FLASH
129 * NAND Flash configuration
131 #define CONFIG_SYS_MAX_NAND_DEVICE 1
133 #define BOOTFLASH_START 0x0
135 /* Kirkwood has two serial IF */
136 #if (CONFIG_CONS_INDEX == 2)
137 #define CONFIG_KM_CONSOLE_TTY "ttyS1"
139 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
143 * Other required minimal configurations
145 #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
146 #define CONFIG_NR_DRAM_BANKS 4
147 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
150 * Ethernet Driver configuration
152 #define CONFIG_NETCONSOLE /* include NetConsole support */
153 #define CONFIG_MII /* expose smi ove miiphy interface */
154 #define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
155 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
156 #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
157 #define CONFIG_PHY_BASE_ADR 0
158 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
159 #define CONFIG_KM_COMMON_ETH_INIT /* standard km ethernet_present for piggy */
164 #define CONFIG_SYS_USE_UBI
169 #undef CONFIG_I2C_MVTWSI
170 #define CONFIG_SYS_I2C
171 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
172 #define CONFIG_SYS_I2C_INIT_BOARD
174 #define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */
175 #define CONFIG_SYS_NUM_I2C_BUSES 6
176 #define CONFIG_SYS_I2C_MAX_HOPS 1
177 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
178 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
179 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
180 {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
181 {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
182 {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
186 #include <asm/arch/gpio.h>
187 extern void __set_direction(unsigned pin, int high);
188 void set_sda(int state);
189 void set_scl(int state);
192 #define KM_KIRKWOOD_SDA_PIN 8
193 #define KM_KIRKWOOD_SCL_PIN 9
194 #define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300
195 #define KM_KIRKWOOD_ENV_WP 38
197 #define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0)
198 #define I2C_TRISTATE __set_direction(KM_KIRKWOOD_SDA_PIN, 1)
199 #define I2C_READ (kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0)
200 #define I2C_SDA(bit) kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit)
201 #define I2C_SCL(bit) kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit)
204 #define I2C_DELAY udelay(1)
205 #define I2C_SOFT_DECLARATIONS
207 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x0
208 #define CONFIG_SYS_I2C_SOFT_SPEED 100000
210 /* EEprom support 24C128, 24C256 valid for environment eeprom */
211 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
212 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 Byte write page */
213 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
215 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
216 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
219 * Environment variables configurations
221 #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
222 #define CONFIG_ENV_IS_IN_SPI_FLASH /* use SPI-Flash for environment vars */
223 #define CONFIG_ENV_OFFSET 0xc0000 /* no bracets! */
224 #define CONFIG_ENV_SIZE 0x02000 /* Size of Environment */
225 #define CONFIG_ENV_SECT_SIZE 0x10000
226 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
227 CONFIG_ENV_SECT_SIZE)
228 #define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */
230 #define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */
231 #define CONFIG_SYS_DEF_EEPROM_ADDR 0x50
232 #define CONFIG_ENV_EEPROM_IS_ON_I2C
233 #define CONFIG_SYS_EEPROM_WREN
234 #define CONFIG_ENV_OFFSET 0x0 /* no bracets! */
235 #define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET)
236 #define CONFIG_I2C_ENV_EEPROM_BUS 5 /* I2C2 (Mux-Port 5) */
237 #define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */
238 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
241 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
244 /* SPI bus claim MPP configuration */
245 #define CONFIG_SYS_KW_SPI_MPP 0x0
247 #define FLASH_GPIO_PIN 0x00010000
248 #define KM_FLASH_GPIO_PIN 16
250 #ifndef MTDIDS_DEFAULT
251 # define MTDIDS_DEFAULT "nand0=orion_nand"
252 #endif /* MTDIDS_DEFAULT */
254 #ifndef MTDPARTS_DEFAULT
255 # define MTDPARTS_DEFAULT "mtdparts=" \
257 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
258 #endif /* MTDPARTS_DEFAULT */
260 #define CONFIG_KM_UPDATE_UBOOT \
262 "sf probe 0;sf erase 0 +${filesize};" \
263 "sf write ${load_addr_r} 0 ${filesize};\0"
265 #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
266 #define CONFIG_KM_NEW_ENV \
267 "newenv=sf probe 0;" \
268 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
269 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
271 #define CONFIG_KM_NEW_ENV \
272 "newenv=setenv addr 0x100000 && " \
273 "i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; " \
274 "mw.b ${addr} 0 4 && " \
275 "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \
276 " ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && " \
277 "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \
278 " ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0"
281 #ifndef CONFIG_KM_BOARD_EXTRA_ENV
282 #define CONFIG_KM_BOARD_EXTRA_ENV ""
286 * Default environment variables
288 #define CONFIG_EXTRA_ENV_SETTINGS \
289 CONFIG_KM_BOARD_EXTRA_ENV \
295 #if defined(CONFIG_SYS_NO_FLASH)
296 #undef CONFIG_FLASH_CFI_MTD
297 #undef CONFIG_JFFS2_CMDLINE
300 /* additions for new relocation code, must be added to all boards */
301 #define CONFIG_SYS_SDRAM_BASE 0x00000000
302 /* Do early setups now in board_init_f() */
305 * resereved pram area at the end of memroy [hex]
306 * 8Mbytes for switch + 4Kbytes for bootcount
308 #define CONFIG_KM_RESERVED_PRAM 0x801000
309 /* address for the bootcount (taken from end of RAM) */
310 #define BOOTCOUNT_ADDR (CONFIG_KM_RESERVED_PRAM)
311 /* Use generic bootcount RAM driver */
312 #define CONFIG_BOOTCOUNT_RAM
314 /* enable POST tests */
315 #define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS)
316 #define CONFIG_POST_SKIP_ENV_FLAGS
317 #define CONFIG_POST_EXTERNAL_WORD_FUNCS
318 #define CONFIG_CMD_DIAG
320 /* we do the whole PCIe FPGA config stuff here */
322 #endif /* _CONFIG_KM_ARM_H */