Merge remote-tracking branch 'u-boot-ti/master'
[platform/kernel/u-boot.git] / include / configs / km / km8309-common.h
1 /*
2  * Copyright (C) 2012 Keymile AG
3  *                    Gerlando Falauto <gerlando.falauto@keymile.com>
4  *
5  * Based on km8321-common.h, see respective copyright notice for credits
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  */
12
13 #ifndef __CONFIG_KM8309_COMMON_H
14 #define __CONFIG_KM8309_COMMON_H
15
16 /*
17  * High Level Configuration Options
18  */
19 #define CONFIG_E300             1       /* E300 family */
20 #define CONFIG_QE               1       /* Has QE */
21 #define CONFIG_MPC83xx          1       /* MPC83xx family */
22 #define CONFIG_MPC830x          1       /* MPC830x family */
23 #define CONFIG_MPC8309          1       /* MPC8309 CPU specific */
24
25 #define CONFIG_KM_DEF_ARCH      "arch=ppc_8xx\0"
26 #define CONFIG_CMD_DIAG         1
27
28 /* include common defines/options for all 83xx Keymile boards */
29 #include "km83xx-common.h"
30
31 /* QE microcode/firmware address */
32 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
33 /* at end of uboot partition, before env */
34 #define CONFIG_SYS_QE_FMAN_FW_ADDR   0xF00B0000
35
36 #define CONFIG_MISC_INIT_R
37
38 /*
39  * System IO Config
40  */
41 /* 0x14000180 SICR_1 */
42 #define CONFIG_SYS_SICRL (0                     \
43                 | SICR_1_UART1_UART1RTS         \
44                 | SICR_1_I2C_CKSTOP             \
45                 | SICR_1_IRQ_A_IRQ              \
46                 | SICR_1_IRQ_B_IRQ              \
47                 | SICR_1_GPIO_A_GPIO            \
48                 | SICR_1_GPIO_B_GPIO            \
49                 | SICR_1_GPIO_C_GPIO            \
50                 | SICR_1_GPIO_D_GPIO            \
51                 | SICR_1_GPIO_E_GPIO            \
52                 | SICR_1_GPIO_F_GPIO            \
53                 | SICR_1_USB_A_UART2S           \
54                 | SICR_1_USB_B_UART2RTS         \
55                 | SICR_1_FEC1_FEC1              \
56                 | SICR_1_FEC2_FEC2              \
57                 )
58
59 /* 0x00080400 SICR_2 */
60 #define CONFIG_SYS_SICRH (0                     \
61                 | SICR_2_FEC3_FEC3              \
62                 | SICR_2_HDLC1_A_HDLC1          \
63                 | SICR_2_ELBC_A_LA              \
64                 | SICR_2_ELBC_B_LCLK            \
65                 | SICR_2_HDLC2_A_HDLC2          \
66                 | SICR_2_USB_D_GPIO             \
67                 | SICR_2_PCI_PCI                \
68                 | SICR_2_HDLC1_B_HDLC1          \
69                 | SICR_2_HDLC1_C_HDLC1          \
70                 | SICR_2_HDLC2_B_GPIO           \
71                 | SICR_2_HDLC2_C_HDLC2          \
72                 | SICR_2_QUIESCE_B              \
73                 )
74
75 /* GPR_1 */
76 #define CONFIG_SYS_GPR1  0x50008060
77
78 #define CONFIG_SYS_GP1DIR 0x00000000
79 #define CONFIG_SYS_GP1ODR 0x00000000
80 #define CONFIG_SYS_GP2DIR 0xFF000000
81 #define CONFIG_SYS_GP2ODR 0x00000000
82
83 /*
84  * Hardware Reset Configuration Word
85  */
86 #define CONFIG_SYS_HRCW_LOW (\
87         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
88         HRCWL_DDR_TO_SCB_CLK_2X1 | \
89         HRCWL_CSB_TO_CLKIN_2X1 | \
90         HRCWL_CORE_TO_CSB_2X1 | \
91         HRCWL_CE_PLL_VCO_DIV_2 | \
92         HRCWL_CE_TO_PLL_1X3)
93
94 #define CONFIG_SYS_HRCW_HIGH (\
95         HRCWH_PCI_AGENT | \
96         HRCWH_PCI_ARBITER_DISABLE | \
97         HRCWH_CORE_ENABLE | \
98         HRCWH_FROM_0X00000100 | \
99         HRCWH_BOOTSEQ_DISABLE | \
100         HRCWH_SW_WATCHDOG_DISABLE | \
101         HRCWH_ROM_LOC_LOCAL_16BIT | \
102         HRCWH_BIG_ENDIAN | \
103         HRCWH_LALE_NORMAL)
104
105 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
106 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
107                                          SDRAM_CFG_32_BE | \
108                                          SDRAM_CFG_SREN | \
109                                          SDRAM_CFG_HSE)
110
111 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
112 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
113 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
114                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
115
116 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
117                                          CSCONFIG_ODT_RD_NEVER | \
118                                          CSCONFIG_ODT_WR_ONLY_CURRENT | \
119                                          CSCONFIG_ROW_BIT_13 | \
120                                          CSCONFIG_COL_BIT_10)
121
122 #define CONFIG_SYS_DDR_MODE     0x47860242
123 #define CONFIG_SYS_DDR_MODE2    0x8080c000
124
125 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
126                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
127                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
128                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
129                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
130                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
131                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
132                                  (0 << TIMING_CFG0_RWT_SHIFT))
133
134 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
135                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
136                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
137                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
138                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
139                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
140                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
141                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
142
143 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
144                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
145                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
146                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
147                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
148                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
149                                  (5 << TIMING_CFG2_CPO_SHIFT))
150
151 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
152
153 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
154 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
155
156 /* EEprom support */
157 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
158
159 /*
160  * Local Bus Configuration & Clock Setup
161  */
162 #define CONFIG_SYS_LCRR_DBYP    0x80000000
163 #define CONFIG_SYS_LCRR_EADC    0x00010000
164 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
165
166 #define CONFIG_SYS_LBC_LBCR     0x00000000
167
168 /*
169  * MMU Setup
170  */
171 #define CONFIG_SYS_IBAT7L       (0)
172 #define CONFIG_SYS_IBAT7U       (0)
173 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
174 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
175
176 #endif /* __CONFIG_KM8309_COMMON_H */