3bd334c515216c4d7f1640949583ae04685a0dfc
[platform/kernel/u-boot.git] / include / configs / km / km8309-common.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2012 Keymile AG
4  *                    Gerlando Falauto <gerlando.falauto@keymile.com>
5  *
6  * Based on km8321-common.h, see respective copyright notice for credits
7  */
8
9 #ifndef __CONFIG_KM8309_COMMON_H
10 #define __CONFIG_KM8309_COMMON_H
11
12 /*
13  * High Level Configuration Options
14  */
15 #define CONFIG_E300             1       /* E300 family */
16 #define CONFIG_QE               1       /* Has QE */
17
18 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
19
20 /* include common defines/options for all 83xx Keymile boards */
21 #include "km83xx-common.h"
22
23 /* QE microcode/firmware address */
24 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
25 /* between the u-boot partition and env */
26 #ifndef CONFIG_SYS_QE_FW_ADDR
27 #define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
28 #endif
29
30 /*
31  * System IO Config
32  */
33 /* 0x14000180 SICR_1 */
34 #define CONFIG_SYS_SICRL (0                     \
35                 | SICR_1_UART1_UART1RTS         \
36                 | SICR_1_I2C_CKSTOP             \
37                 | SICR_1_IRQ_A_IRQ              \
38                 | SICR_1_IRQ_B_IRQ              \
39                 | SICR_1_GPIO_A_GPIO            \
40                 | SICR_1_GPIO_B_GPIO            \
41                 | SICR_1_GPIO_C_GPIO            \
42                 | SICR_1_GPIO_D_GPIO            \
43                 | SICR_1_GPIO_E_GPIO            \
44                 | SICR_1_GPIO_F_GPIO            \
45                 | SICR_1_USB_A_UART2S           \
46                 | SICR_1_USB_B_UART2RTS         \
47                 | SICR_1_FEC1_FEC1              \
48                 | SICR_1_FEC2_FEC2              \
49                 )
50
51 /* 0x00080400 SICR_2 */
52 #define CONFIG_SYS_SICRH (0                     \
53                 | SICR_2_FEC3_FEC3              \
54                 | SICR_2_HDLC1_A_HDLC1          \
55                 | SICR_2_ELBC_A_LA              \
56                 | SICR_2_ELBC_B_LCLK            \
57                 | SICR_2_HDLC2_A_HDLC2          \
58                 | SICR_2_USB_D_GPIO             \
59                 | SICR_2_PCI_PCI                \
60                 | SICR_2_HDLC1_B_HDLC1          \
61                 | SICR_2_HDLC1_C_HDLC1          \
62                 | SICR_2_HDLC2_B_GPIO           \
63                 | SICR_2_HDLC2_C_HDLC2          \
64                 | SICR_2_QUIESCE_B              \
65                 )
66
67 /* GPR_1 */
68 #define CONFIG_SYS_GPR1  0x50008060
69
70 #define CONFIG_SYS_GP1DIR 0x00000000
71 #define CONFIG_SYS_GP1ODR 0x00000000
72 #define CONFIG_SYS_GP2DIR 0xFF000000
73 #define CONFIG_SYS_GP2ODR 0x00000000
74
75 /*
76  * Hardware Reset Configuration Word
77  */
78 #define CONFIG_SYS_HRCW_LOW (\
79         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
80         HRCWL_DDR_TO_SCB_CLK_2X1 | \
81         HRCWL_CSB_TO_CLKIN_2X1 | \
82         HRCWL_CORE_TO_CSB_2X1 | \
83         HRCWL_CE_PLL_VCO_DIV_2 | \
84         HRCWL_CE_TO_PLL_1X3)
85
86 #define CONFIG_SYS_HRCW_HIGH (\
87         HRCWH_PCI_AGENT | \
88         HRCWH_PCI_ARBITER_DISABLE | \
89         HRCWH_CORE_ENABLE | \
90         HRCWH_FROM_0X00000100 | \
91         HRCWH_BOOTSEQ_DISABLE | \
92         HRCWH_SW_WATCHDOG_DISABLE | \
93         HRCWH_ROM_LOC_LOCAL_16BIT | \
94         HRCWH_BIG_ENDIAN | \
95         HRCWH_LALE_NORMAL)
96
97 #define CONFIG_SYS_DDRCDR (\
98         DDRCDR_EN | \
99         DDRCDR_PZ_MAXZ | \
100         DDRCDR_NZ_MAXZ | \
101         DDRCDR_M_ODR)
102
103 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
104 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
105                                          SDRAM_CFG_32_BE | \
106                                          SDRAM_CFG_SREN | \
107                                          SDRAM_CFG_HSE)
108
109 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
110 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
111 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
112                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
113
114 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
115                                          CSCONFIG_ODT_RD_NEVER | \
116                                          CSCONFIG_ODT_WR_ONLY_CURRENT | \
117                                          CSCONFIG_ROW_BIT_13 | \
118                                          CSCONFIG_COL_BIT_10)
119
120 #define CONFIG_SYS_DDR_MODE     0x47860242
121 #define CONFIG_SYS_DDR_MODE2    0x8080c000
122
123 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
124                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
125                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
126                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
127                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
128                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
129                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
130                                  (0 << TIMING_CFG0_RWT_SHIFT))
131
132 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
133                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
134                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
135                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
136                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
137                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
138                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
139                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
140
141 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
142                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
143                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
144                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
145                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
146                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
147                                  (5 << TIMING_CFG2_CPO_SHIFT))
148
149 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
150
151 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
152 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
153
154 /* EEprom support */
155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
156
157 /*
158  * Local Bus Configuration & Clock Setup
159  */
160 #define CONFIG_SYS_LCRR_DBYP    0x80000000
161 #define CONFIG_SYS_LCRR_EADC    0x00010000
162 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
163
164 #define CONFIG_SYS_LBC_LBCR     0x00000000
165
166 /*
167  * MMU Setup
168  */
169 #define CONFIG_SYS_IBAT7L       (0)
170 #define CONFIG_SYS_IBAT7U       (0)
171 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
172 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
173
174 #endif /* __CONFIG_KM8309_COMMON_H */