include/configs/km/km82xx-common.h

   1 /*
   2  * (C) Copyright 2007-2010
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __KM82XX_COMMON
  25 #define __KM82XX_COMMON
  26
  27 /*
  28  * Select serial console configuration
  29  *
  30  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  31  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  32  * for SCC).
  33  */
  34 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
  35 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
  36 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
  37 #define CONFIG_CONS_INDEX       2       /* SMC2 is used for console  */
  38 #define CONFIG_SYS_SMC_RXBUFLEN 128
  39 #define CONFIG_SYS_MAXIDLE      10
  40
  41 /*
  42  * Select ethernet configuration
  43  *
  44  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  45  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  46  * SCC, 1-3 for FCC)
  47  *
  48  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  49  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
  50  * must be unset.
  51  */
  52 #define CONFIG_ETHER_ON_SCC             /* Ethernet is on SCC */
  53 #undef  CONFIG_ETHER_ON_FCC             /* Ethernet is not on FCC     */
  54 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
  55
  56 #define CONFIG_ETHER_INDEX      4
  57 #define CONFIG_HAS_ETH0
  58 #define CONFIG_SYS_SCC_TOUT_LOOP        10000000
  59
  60 #define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
  61
  62 #ifndef CONFIG_8260_CLKIN
  63 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
  64 #endif
  65
  66 #define BOOTFLASH_START         0xFE000000
  67
  68 #define CONFIG_KM_CONSOLE_TTY   "ttyCPM0"
  69
  70 #define MTDPARTS_DEFAULT        "mtdparts="                             \
  71         "app:"                                                          \
  72                 "768k(u-boot),"                                         \
  73                 "128k(env),"                                            \
  74                 "128k(envred),"                                         \
  75                 "3072k(free),"                                          \
  76                 "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
  77
  78 /*
  79  * Default environment settings
  80  */
  81 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  82         CONFIG_KM_BOARD_EXTRA_ENV                                       \
  83         CONFIG_KM_DEF_ENV                                               \
  84         "EEprom_ivm=pca9544a:70:4 \0"                                   \
  85         "unlock=yes\0"                                                  \
  86         "newenv="                                                       \
  87                 "prot off 0xFE0C0000 +0x40000 && "                      \
  88                 "era 0xFE0C0000 +0x40000\0"                             \
  89         "arch=ppc_82xx\0"                                       \
  90         ""
  91
  92 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  93 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  94 #define CONFIG_SYS_RAMBOOT
  95 #endif
  96
  97 #define CONFIG_SYS_MONITOR_LEN          (768 << 10)
  98
  99 #define CONFIG_ENV_IS_IN_FLASH
 100
 101 #ifdef CONFIG_ENV_IS_IN_FLASH
 102 #define CONFIG_ENV_SECT_SIZE    0x20000
 103 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 104                                         CONFIG_SYS_MONITOR_LEN)
 105 #define CONFIG_ENV_OFFSET       CONFIG_SYS_MONITOR_LEN
 106
 107 /* Address and size of Redundant Environment Sector     */
 108 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 109                                                 CONFIG_ENV_SECT_SIZE)
 110 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
 111 #endif /* CONFIG_ENV_IS_IN_FLASH */
 112
 113 /* enable I2C and select the hardware/software driver */
 114 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 115 #define CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 116 #define CONFIG_SYS_I2C_SPEED            50000   /* I2C speed */
 117 #define CONFIG_SYS_I2C_SLAVE            0x7F    /* I2C slave address */
 118
 119 /*
 120  * Software (bit-bang) I2C driver configuration
 121  */
 122
 123 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 124 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 125 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 126 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 127 #define I2C_SDA(bit)    do { \
 128                                 if (bit) \
 129                                         iop->pdat |=  0x00010000; \
 130                                 else \
 131                                         iop->pdat &= ~0x00010000; \
 132                         } while (0)
 133 #define I2C_SCL(bit)    do { \
 134                                 if (bit) \
 135                                         iop->pdat |=  0x00020000; \
 136                                 else \
 137                                         iop->pdat &= ~0x00020000; \
 138                         } while (0)
 139 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 140
 141 #ifndef __ASSEMBLY__
 142 void set_sda(int state);
 143 void set_scl(int state);
 144 int get_sda(void);
 145 int get_scl(void);
 146 #endif
 147
 148 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 149 #define CONFIG_DTT_LM75                 /* ON Semi's LM75               */
 150 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
 151 #define CONFIG_SYS_DTT_MAX_TEMP 70
 152 #define CONFIG_SYS_DTT_LOW_TEMP -30
 153 #define CONFIG_SYS_DTT_HYSTERESIS       3
 154 #define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
 155
 156 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 157
 158 #define CONFIG_SYS_IMMR         0xF0000000
 159
 160 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 161 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000 /* used size in DPRAM */
 162 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 163                                                 GENERATED_GBL_DATA_SIZE)
 164 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 165
 166 /* Hard reset configuration word */
 167 #define CONFIG_SYS_HRCW_MASTER          0x0604b211
 168
 169 /* No slaves */
 170 #define CONFIG_SYS_HRCW_SLAVE1          0
 171 #define CONFIG_SYS_HRCW_SLAVE2          0
 172 #define CONFIG_SYS_HRCW_SLAVE3          0
 173 #define CONFIG_SYS_HRCW_SLAVE4          0
 174 #define CONFIG_SYS_HRCW_SLAVE5          0
 175 #define CONFIG_SYS_HRCW_SLAVE6          0
 176 #define CONFIG_SYS_HRCW_SLAVE7          0
 177
 178 /* Initial Memory map for Linux */
 179 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 180
 181 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
 182 #if defined(CONFIG_CMD_KGDB)
 183 #  define CONFIG_SYS_CACHELINE_SHIFT    5 /* log base 2 of the above value */
 184 #endif
 185
 186 #define CONFIG_SYS_HID0_INIT            0
 187 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
 188
 189 #define CONFIG_SYS_HID2         0
 190
 191 #define CONFIG_SYS_SIUMCR               0x4020c200
 192 #define CONFIG_SYS_SYPCR                0xFFFFFF83
 193 #define CONFIG_SYS_BCR                  0x10000000
 194 #define CONFIG_SYS_SCCR         (SCCR_PCI_MODE | SCCR_PCI_MODCK)
 195
 196 /*
 197  *-----------------------------------------------------------------------
 198  * RMR - Reset Mode Register                                     5-5
 199  *-----------------------------------------------------------------------
 200  * turn on Checkstop Reset Enable
 201  */
 202 #define CONFIG_SYS_RMR         0
 203
 204 /*
 205  *-----------------------------------------------------------------------
 206  * TMCNTSC - Time Counter Status and Control                     4-40
 207  *-----------------------------------------------------------------------
 208  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 209  * and enable Time Counter
 210  */
 211 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 212
 213 /*
 214  *-----------------------------------------------------------------------
 215  * PISCR - Periodic Interrupt Status and Control                 4-42
 216  *-----------------------------------------------------------------------
 217  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 218  * Periodic timer
 219  */
 220 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 221
 222 /*
 223  *-----------------------------------------------------------------------
 224  * RCCR - RISC Controller Configuration                         13-7
 225  *-----------------------------------------------------------------------
 226  */
 227 #define CONFIG_SYS_RCCR        0
 228
 229 /*
 230  * Init Memory Controller:
 231  *
 232  * Bank Bus     Machine PortSz  Device
 233  * ---- ---     ------- ------  ------
 234  *  0   60x     GPCM     8 bit  FLASH
 235  *  1   60x     SDRAM   32 bit  SDRAM
 236  *  3   60x     GPCM     8 bit  GPIO/PIGGY
 237  *  5   60x     GPCM    16 bit  CFG-Flash
 238  *
 239  */
 240 /* Bank 0 - FLASH
 241  */
 242 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)    |\
 243                          BRx_PS_8                       |\
 244                          BRx_MS_GPCM_P                  |\
 245                          BRx_V)
 246
 247 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)        |\
 248                          ORxG_CSNT                      |\
 249                          ORxG_ACS_DIV2                  |\
 250                          ORxG_SCY_5_CLK                 |\
 251                          ORxG_TRLX)
 252
 253 #define CONFIG_SYS_MPTPR       0x1800
 254
 255 /*
 256  *-----------------------------------------------------------------------------
 257  * Address for Mode Register Set (MRS) command
 258  *-----------------------------------------------------------------------------
 259  */
 260 #define CONFIG_SYS_MRS_OFFS     0x00000110
 261 #define CONFIG_SYS_PSRT        0x0e
 262
 263 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
 264                          BRx_PS_64              |\
 265                          BRx_MS_SDRAM_P         |\
 266                          BRx_V)
 267
 268 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1
 269
 270 /*
 271  * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
 272  */
 273 #define CONFIG_SYS_KMBEC_FPGA_BASE      0x30000000
 274 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 275
 276 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
 277                          BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 278
 279 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
 280                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 281                          ORxG_SCY_3_CLK | ORxG_TRLX)
 282
 283 /*
 284  * BFTICU board FPGA on CS4 initialization values
 285  */
 286 #define CONFIG_SYS_FPGA_BASE    0x40000000
 287 #define CONFIG_SYS_FPGA_SIZE    1 /*1KB*/
 288
 289 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
 290                         BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 291
 292 #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
 293                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 294                          ORxG_SCY_3_CLK | ORxG_TRLX)
 295
 296 /*
 297  * CFG-Flash on CS5 initialization values
 298  */
 299 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
 300                          BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
 301
 302 #define CONFIG_SYS_OR5_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
 303                                  CONFIG_SYS_FLASH_SIZE_2) |\
 304                                  ORxG_CSNT | ORxG_ACS_DIV2 |\
 305                                  ORxG_SCY_5_CLK | ORxG_TRLX)
 306
 307 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC     /* "bad" address */
 308
 309 /* pass open firmware flat tree */
 310 #define CONFIG_FIT              1
 311 #define CONFIG_OF_LIBFDT        1
 312 #define CONFIG_OF_BOARD_SETUP   1
 313
 314 #define OF_TBCLK                (bd->bi_busfreq / 4)
 315 #define OF_STDOUT_PATH          "/soc/cpm/serial@11a90"
 316
 317 #endif /* __KM82XX_COMMON */