include/configs/km/km-mpc8360.h

   1 /* KMBEC FPGA (PRIO) */
   2 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
   3 #define CONFIG_SYS_KMBEC_FPGA_SIZE      64
   4
   5 /*
   6  * High Level Configuration Options
   7  */
   8 #define CONFIG_QE                       /* Has QE */
   9
  10 /*
  11  * QE UEC ethernet configuration
  12  */
  13 #define CONFIG_UEC_ETH1         /* GETH1 */
  14 #define UEC_VERBOSE_DEBUG       1
  15
  16 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
  17 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
  18 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
  19 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
  20 #define CONFIG_SYS_UEC1_PHY_ADDR        0
  21 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
  22 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
  23
  24 /*
  25  * System IO Setup
  26  */
  27 #define CONFIG_SYS_SICRH                (SICRH_UC1EOBI | SICRH_UC2E1OBI)
  28
  29 /**
  30  * DDR RAM settings
  31  */
  32 #define CONFIG_SYS_DDR_SDRAM_CFG (\
  33         SDRAM_CFG_SDRAM_TYPE_DDR2 | \
  34         SDRAM_CFG_SREN | \
  35         SDRAM_CFG_HSE)
  36
  37 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  38
  39 #define CONFIG_SYS_DDR_CLK_CNTL (\
  40         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  41
  42 #define CONFIG_SYS_DDR_INTERVAL (\
  43         (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  44         (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
  45
  46 #define CONFIG_SYS_DDR_CS0_BNDS                 0x0000007f
  47
  48 #define CONFIG_SYS_DDRCDR (\
  49         DDRCDR_EN | \
  50         DDRCDR_Q_DRN)
  51 #define CONFIG_SYS_DDR_MODE             0x47860452
  52 #define CONFIG_SYS_DDR_MODE2            0x8080c000
  53
  54 #define CONFIG_SYS_DDR_TIMING_0 (\
  55         (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  56         (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  57         (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  58         (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  59         (0 << TIMING_CFG0_WWT_SHIFT) | \
  60         (0 << TIMING_CFG0_RRT_SHIFT) | \
  61         (0 << TIMING_CFG0_WRT_SHIFT) | \
  62         (0 << TIMING_CFG0_RWT_SHIFT))
  63
  64 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
  65                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
  66                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
  67                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
  68                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
  69                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
  70                                  (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
  71                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
  72
  73 #define CONFIG_SYS_DDR_TIMING_2 (\
  74         (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
  75         (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
  76         (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
  77         (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
  78         (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
  79         (5 << TIMING_CFG2_CPO_SHIFT) | \
  80         (0 << TIMING_CFG2_ADD_LAT_SHIFT))
  81
  82 #define CONFIG_SYS_DDR_TIMING_3                 0x00000000
  83
  84 /* EEprom support */
  85 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
  86
  87 /*
  88  * PAXE on the local bus CS3
  89  */
  90 #define CONFIG_SYS_PAXE_BASE            0xA0000000
  91 #define CONFIG_SYS_PAXE_SIZE            256