include/configs/km/km-mpc8360.h

   1 /* KMBEC FPGA (PRIO) */
   2 #define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000
   3 #define CFG_SYS_KMBEC_FPGA_SIZE 64
   4
   5 /*
   6  * High Level Configuration Options
   7  */
   8
   9 /*
  10  * System IO Setup
  11  */
  12 #define CFG_SYS_SICRH           (SICRH_UC1EOBI | SICRH_UC2E1OBI)
  13
  14 /**
  15  * DDR RAM settings
  16  */
  17 #define CFG_SYS_DDR_SDRAM_CFG (\
  18         SDRAM_CFG_SDRAM_TYPE_DDR2 | \
  19         SDRAM_CFG_SREN | \
  20         SDRAM_CFG_HSE)
  21
  22 #define CFG_SYS_DDR_SDRAM_CFG2  0x00401000
  23
  24 #define CFG_SYS_DDR_CLK_CNTL (\
  25         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  26
  27 #define CFG_SYS_DDR_INTERVAL (\
  28         (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  29         (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
  30
  31 #define CFG_SYS_DDR_CS0_BNDS                    0x0000007f
  32
  33 #define CFG_SYS_DDRCDR (\
  34         DDRCDR_EN | \
  35         DDRCDR_Q_DRN)
  36 #define CFG_SYS_DDR_MODE                0x47860452
  37 #define CFG_SYS_DDR_MODE2               0x8080c000
  38
  39 #define CFG_SYS_DDR_TIMING_0 (\
  40         (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  41         (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  42         (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  43         (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  44         (0 << TIMING_CFG0_WWT_SHIFT) | \
  45         (0 << TIMING_CFG0_RRT_SHIFT) | \
  46         (0 << TIMING_CFG0_WRT_SHIFT) | \
  47         (0 << TIMING_CFG0_RWT_SHIFT))
  48
  49 #define CFG_SYS_DDR_TIMING_1    ((TIMING_CFG1_CASLAT_50) | \
  50                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
  51                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
  52                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
  53                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
  54                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
  55                                  (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
  56                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
  57
  58 #define CFG_SYS_DDR_TIMING_2 (\
  59         (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
  60         (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
  61         (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
  62         (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
  63         (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
  64         (5 << TIMING_CFG2_CPO_SHIFT) | \
  65         (0 << TIMING_CFG2_ADD_LAT_SHIFT))
  66
  67 #define CFG_SYS_DDR_TIMING_3                    0x00000000
  68