include/configs/km/km-mpc832x.h

   1 /*
   2  * High Level Configuration Options
   3  */
   4 #define CONFIG_QE       /* Has QE */
   5 #define CONFIG_KM8321   /* Keymile PBEC8321 board specific */
   6
   7 /*
   8  * System Clock Setup
   9  */
  10 #define CONFIG_83XX_CLKIN               66000000
  11 #define CONFIG_SYS_CLK_FREQ             66000000
  12 #define CONFIG_83XX_PCICLK              66000000
  13
  14 /*
  15  * QE UEC ethernet configuration
  16  */
  17 #define CONFIG_UEC_ETH1         /* GETH1 */
  18 #define UEC_VERBOSE_DEBUG       1
  19
  20 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
  21 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
  22 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
  23 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
  24 #define CONFIG_SYS_UEC1_PHY_ADDR        0
  25 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
  26 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
  27
  28 /*
  29  * System IO Config
  30  */
  31 #define CONFIG_SYS_SICRL        SICRL_IRQ_CKS
  32
  33 #define CONFIG_SYS_DDRCDR (\
  34         DDRCDR_EN | \
  35         DDRCDR_PZ_MAXZ | \
  36         DDRCDR_NZ_MAXZ | \
  37         DDRCDR_M_ODR)
  38
  39 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
  40 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
  41                                          SDRAM_CFG_32_BE | \
  42                                          SDRAM_CFG_SREN | \
  43                                          SDRAM_CFG_HSE)
  44
  45 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  46 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  47 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  48                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
  49
  50 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
  51                                          CSCONFIG_ODT_WR_CFG | \
  52                                          CSCONFIG_ROW_BIT_13 | \
  53                                          CSCONFIG_COL_BIT_10)
  54
  55 #define CONFIG_SYS_DDR_MODE     0x47860242
  56 #define CONFIG_SYS_DDR_MODE2    0x8080c000
  57
  58 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  59                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  60                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  61                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  62                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
  63                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
  64                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
  65                                  (0 << TIMING_CFG0_RWT_SHIFT))
  66
  67 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
  68                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
  69                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
  70                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
  71                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
  72                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
  73                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
  74                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
  75
  76 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
  77                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
  78                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
  79                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
  80                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
  81                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
  82                                  (5 << TIMING_CFG2_CPO_SHIFT))
  83
  84 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  85
  86 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
  87 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
  88
  89 /* EEprom support */
  90 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
  91