2 * High Level Configuration Options
5 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
7 /* QE microcode/firmware address */
8 /* between the u-boot partition and env */
13 /* 0x14000180 SICR_1 */
14 #ifndef CONFIG_SYS_SICRL
15 #define CONFIG_SYS_SICRL (0 \
16 | SICR_1_UART1_UART1RTS \
20 | SICR_1_GPIO_A_GPIO \
21 | SICR_1_GPIO_B_GPIO \
22 | SICR_1_GPIO_C_GPIO \
23 | SICR_1_GPIO_D_GPIO \
24 | SICR_1_GPIO_E_GPIO \
25 | SICR_1_GPIO_F_GPIO \
26 | SICR_1_USB_A_UART2S \
27 | SICR_1_USB_B_UART2RTS \
33 /* 0x00080400 SICR_2 */
34 #define CONFIG_SYS_SICRH (0 \
36 | SICR_2_HDLC1_A_HDLC1 \
38 | SICR_2_ELBC_B_LCLK \
39 | SICR_2_HDLC2_A_HDLC2 \
42 | SICR_2_HDLC1_B_HDLC1 \
43 | SICR_2_HDLC1_C_HDLC1 \
44 | SICR_2_HDLC2_B_GPIO \
45 | SICR_2_HDLC2_C_HDLC2 \
50 #define CONFIG_SYS_GPR1 0x50008060
52 #define CONFIG_SYS_GP1DIR 0x00000000
53 #define CONFIG_SYS_GP1ODR 0x00000000
54 #define CONFIG_SYS_GP2DIR 0xFF000000
55 #define CONFIG_SYS_GP2ODR 0x00000000
57 #define CONFIG_SYS_DDRCDR (\
63 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
64 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
69 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
70 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
71 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
72 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
74 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
75 CSCONFIG_ODT_RD_NEVER | \
76 CSCONFIG_ODT_WR_ONLY_CURRENT | \
77 CSCONFIG_ROW_BIT_13 | \
80 #define CONFIG_SYS_DDR_MODE 0x47860242
81 #define CONFIG_SYS_DDR_MODE2 0x8080c000
83 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
84 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
85 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
86 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
87 (0 << TIMING_CFG0_WWT_SHIFT) | \
88 (0 << TIMING_CFG0_RRT_SHIFT) | \
89 (0 << TIMING_CFG0_WRT_SHIFT) | \
90 (0 << TIMING_CFG0_RWT_SHIFT))
92 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
93 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
94 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
95 (3 << TIMING_CFG1_WRREC_SHIFT) | \
96 (7 << TIMING_CFG1_REFREC_SHIFT) | \
97 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
98 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
99 (3 << TIMING_CFG1_PRETOACT_SHIFT))
101 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
102 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
103 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
104 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
105 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
106 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
107 (5 << TIMING_CFG2_CPO_SHIFT))
109 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
111 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
112 #define CONFIG_SYS_KMBEC_FPGA_SIZE 128
116 /* ethernet port connected to piggy (UEC2) */
117 #define CONFIG_UEC_ETH2
118 #define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
119 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
120 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
121 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
122 #define CONFIG_SYS_UEC2_PHY_ADDR 0
123 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
124 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100