include/configs/km/km-mpc8309.h

   1 /*
   2  * High Level Configuration Options
   3  */
   4 #define CONFIG_E300             1       /* E300 family */
   5
   6 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
   7
   8 /* QE microcode/firmware address */
   9 /* between the u-boot partition and env */
  10
  11 /*
  12  * System IO Config
  13  */
  14 /* 0x14000180 SICR_1 */
  15 #ifndef CONFIG_SYS_SICRL
  16 #define CONFIG_SYS_SICRL (0                     \
  17                 | SICR_1_UART1_UART1RTS         \
  18                 | SICR_1_I2C_CKSTOP             \
  19                 | SICR_1_IRQ_A_IRQ              \
  20                 | SICR_1_IRQ_B_IRQ              \
  21                 | SICR_1_GPIO_A_GPIO            \
  22                 | SICR_1_GPIO_B_GPIO            \
  23                 | SICR_1_GPIO_C_GPIO            \
  24                 | SICR_1_GPIO_D_GPIO            \
  25                 | SICR_1_GPIO_E_GPIO            \
  26                 | SICR_1_GPIO_F_GPIO            \
  27                 | SICR_1_USB_A_UART2S           \
  28                 | SICR_1_USB_B_UART2RTS         \
  29                 | SICR_1_FEC1_FEC1              \
  30                 | SICR_1_FEC2_FEC2              \
  31                 )
  32 #endif
  33
  34 /* 0x00080400 SICR_2 */
  35 #define CONFIG_SYS_SICRH (0                     \
  36                 | SICR_2_FEC3_FEC3              \
  37                 | SICR_2_HDLC1_A_HDLC1          \
  38                 | SICR_2_ELBC_A_LA              \
  39                 | SICR_2_ELBC_B_LCLK            \
  40                 | SICR_2_HDLC2_A_HDLC2          \
  41                 | SICR_2_USB_D_GPIO             \
  42                 | SICR_2_PCI_PCI                \
  43                 | SICR_2_HDLC1_B_HDLC1          \
  44                 | SICR_2_HDLC1_C_HDLC1          \
  45                 | SICR_2_HDLC2_B_GPIO           \
  46                 | SICR_2_HDLC2_C_HDLC2          \
  47                 | SICR_2_QUIESCE_B              \
  48                 )
  49
  50 /* GPR_1 */
  51 #define CONFIG_SYS_GPR1  0x50008060
  52
  53 #define CONFIG_SYS_GP1DIR 0x00000000
  54 #define CONFIG_SYS_GP1ODR 0x00000000
  55 #define CONFIG_SYS_GP2DIR 0xFF000000
  56 #define CONFIG_SYS_GP2ODR 0x00000000
  57
  58 #define CONFIG_SYS_DDRCDR (\
  59         DDRCDR_EN | \
  60         DDRCDR_PZ_MAXZ | \
  61         DDRCDR_NZ_MAXZ | \
  62         DDRCDR_M_ODR)
  63
  64 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
  65 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
  66                                          SDRAM_CFG_32_BE | \
  67                                          SDRAM_CFG_SREN | \
  68                                          SDRAM_CFG_HSE)
  69
  70 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  71 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  72 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  73                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
  74
  75 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
  76                                          CSCONFIG_ODT_RD_NEVER | \
  77                                          CSCONFIG_ODT_WR_ONLY_CURRENT | \
  78                                          CSCONFIG_ROW_BIT_13 | \
  79                                          CSCONFIG_COL_BIT_10)
  80
  81 #define CONFIG_SYS_DDR_MODE     0x47860242
  82 #define CONFIG_SYS_DDR_MODE2    0x8080c000
  83
  84 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  85                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  86                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  87                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  88                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
  89                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
  90                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
  91                                  (0 << TIMING_CFG0_RWT_SHIFT))
  92
  93 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
  94                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
  95                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
  96                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
  97                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
  98                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
  99                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 100                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 101
 102 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 103                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 104                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 105                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 106                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 107                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 108                                  (5 << TIMING_CFG2_CPO_SHIFT))
 109
 110 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 111
 112 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 113 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 114
 115 /* EEprom support */
 116
 117 /* ethernet port connected to piggy (UEC2) */
 118 #define CONFIG_UEC_ETH2
 119 #define CONFIG_SYS_UEC2_UCC_NUM         2       /* UCC3 */
 120 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 121 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK12
 122 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 123 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 124 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 125 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100