Merge branch 'master' of git://git.denx.de/u-boot-cfi-flash
[platform/kernel/u-boot.git] / include / configs / kilauea.h
1 /*
2  * Copyright (c) 2008 Nuovation System Designs, LLC
3  *   Grant Erickson <gerickson@nuovations.com>
4  *
5  * (C) Copyright 2007
6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  */
26
27 /************************************************************************
28  * kilauea.h - configuration for AMCC Kilauea (405EX)
29  ***********************************************************************/
30
31 #ifndef __CONFIG_H
32 #define __CONFIG_H
33
34 /*-----------------------------------------------------------------------
35  * High Level Configuration Options
36  *----------------------------------------------------------------------*/
37 #define CONFIG_KILAUEA          1               /* Board is Kilauea     */
38 #define CONFIG_4xx              1               /* ... PPC4xx family    */
39 #define CONFIG_405EX            1               /* Specifc 405EX support*/
40 #define CONFIG_SYS_CLK_FREQ     33333333        /* ext frequency to pll */
41
42 #ifndef CONFIG_SYS_TEXT_BASE
43 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
44 #endif
45
46 /*
47  * CHIP_21 errata - you must set this to match your exact CPU, else your
48  * board will not boot.  DO NOT enable this unless you have JTAG available
49  * for recovery, in the event you get it wrong.
50  *
51  * Kilauea uses the 405EX, while Haleakala uses the 405EXr.  Either board
52  * may be equipped for security or not.  You must look at the CPU part
53  * number to be sure what you have.
54  */
55 /* #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY */
56 /* #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY */
57 /* #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY */
58 /* #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY */
59
60 /*
61  * Include common defines/options for all AMCC eval boards
62  */
63 #define CONFIG_HOSTNAME         kilauea
64 #include "amcc-common.h"
65
66 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
67 #define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
68 #define CONFIG_BOARD_TYPES
69 #define CONFIG_BOARD_EMAC_COUNT
70
71 /*-----------------------------------------------------------------------
72  * Base addresses -- Note these are effective addresses where the
73  * actual resources get mapped (not physical addresses)
74  *----------------------------------------------------------------------*/
75 #define CONFIG_SYS_FLASH_BASE           0xFC000000
76 #define CONFIG_SYS_NAND_ADDR            0xF8000000
77 #define CONFIG_SYS_FPGA_BASE            0xF0000000
78
79 /*-----------------------------------------------------------------------
80  * Initial RAM & Stack Pointer Configuration Options
81  *
82  *   There are traditionally three options for the primordial
83  *   (i.e. initial) stack usage on the 405-series:
84  *
85  *      1) On-chip Memory (OCM) (i.e. SRAM)
86  *      2) Data cache
87  *      3) SDRAM
88  *
89  *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
90  *   the latter of which is less than desireable since it requires
91  *   setting up the SDRAM and ECC in assembly code.
92  *
93  *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
94  *   select on the External Bus Controller (EBC) and then select a
95  *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
96  *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
97  *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
98  *   physical SDRAM to use (3).
99  *-----------------------------------------------------------------------*/
100
101 #define CONFIG_SYS_INIT_DCACHE_CS       4
102
103 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
104 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + ( 1 << 30))    /*  1 GiB */
105 #else
106 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + (32 << 20))    /* 32 MiB */
107 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
108
109 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)                       /*  4 KiB */
110 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
111
112 /*
113  * If the data cache is being used for the primordial stack and global
114  * data area, the POST word must be placed somewhere else. The General
115  * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
116  * its compare and mask register contents across reset, so it is used
117  * for the POST word.
118  */
119
120 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
121 # define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
122 # define CONFIG_SYS_POST_WORD_ADDR      (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
123 #else
124 # define CONFIG_SYS_INIT_EXTRA_SIZE     16
125 # define CONFIG_SYS_INIT_SP_OFFSET      (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
126 # define CONFIG_SYS_OCM_DATA_ADDR       CONFIG_SYS_INIT_RAM_ADDR
127 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
128
129 /*-----------------------------------------------------------------------
130  * Serial Port
131  *----------------------------------------------------------------------*/
132 #define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200        /* ext. 11.059MHz clk   */
133 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
134
135 /*-----------------------------------------------------------------------
136  * Environment
137  *----------------------------------------------------------------------*/
138 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
139 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
140 #else
141 #define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars        */
142 #define CONFIG_ENV_IS_EMBEDDED  1       /* use embedded environment */
143 #endif
144
145 /*-----------------------------------------------------------------------
146  * FLASH related
147  *----------------------------------------------------------------------*/
148 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
149 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
150
151 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
152 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
153 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
154
155 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
156 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
157
158 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
159 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
160
161 #ifdef CONFIG_ENV_IS_IN_FLASH
162 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
163 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
164 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
165
166 /* Address and size of Redundant Environment Sector     */
167 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
168 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
169 #endif /* CONFIG_ENV_IS_IN_FLASH */
170
171 /*
172  * IPL (Initial Program Loader, integrated inside CPU)
173  * Will load first 4k from NAND (SPL) into cache and execute it from there.
174  *
175  * SPL (Secondary Program Loader)
176  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
177  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
178  * controller and the NAND controller so that the special U-Boot image can be
179  * loaded from NAND to SDRAM.
180  *
181  * NUB (NAND U-Boot)
182  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
183  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
184  *
185  * On 405EX the SPL is copied to SDRAM before the NAND controller is
186  * set up. While still running from location 0xfffff000...0xffffffff the
187  * NAND controller cannot be accessed since it is attached to CS0 too.
188  */
189 #define CONFIG_SYS_NAND_BOOT_SPL_SRC    0xfffff000      /* SPL location                 */
190 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE   (4 << 10)       /* SPL size                     */
191 #define CONFIG_SYS_NAND_BOOT_SPL_DST    0x00800000      /* Copy SPL here                */
192 #define CONFIG_SYS_NAND_U_BOOT_DST      0x01000000      /* Load NUB to this addr        */
193 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr  */
194 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA  (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
195
196 /*
197  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
198  */
199 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (16 << 10)      /* Offset to RAM U-Boot image   */
200 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (384 << 10)     /* Size of RAM U-Boot image     */
201
202 /*
203  * Now the NAND chip has to be defined (no autodetection used!)
204  */
205 #define CONFIG_SYS_NAND_PAGE_SIZE       512             /* NAND chip page size          */
206 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10)      /* NAND chip block size         */
207 #define CONFIG_SYS_NAND_PAGE_COUNT      32              /* NAND chip page count         */
208 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   5               /* Location of bad block marker */
209 #define CONFIG_SYS_NAND_4_ADDR_CYCLE    1               /* Fourth addr used (>32MB)     */
210
211 #define CONFIG_SYS_NAND_ECCSIZE 256
212 #define CONFIG_SYS_NAND_ECCBYTES        3
213 #define CONFIG_SYS_NAND_OOBSIZE 16
214 #define CONFIG_SYS_NAND_ECCPOS          {0, 1, 2, 3, 6, 7}
215
216 #ifdef CONFIG_ENV_IS_IN_NAND
217 /*
218  * For NAND booting the environment is embedded in the U-Boot image. Please take
219  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
220  */
221 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
222 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
223 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
224 #endif
225
226 /*-----------------------------------------------------------------------
227  * NAND FLASH
228  *----------------------------------------------------------------------*/
229 #define CONFIG_SYS_MAX_NAND_DEVICE      1
230 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
231 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
232
233 /*-----------------------------------------------------------------------
234  * DDR SDRAM
235  *----------------------------------------------------------------------*/
236 #define CONFIG_SYS_MBYTES_SDRAM        (256)            /* 256MB                        */
237
238 /*
239  * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
240  *
241  * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
242  *       SDRAM Controller DDR autocalibration values and takes a lot longer
243  *       to run than Method_B.
244  * (See the Method_A and Method_B algorithm discription in the file:
245  *      arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
246  * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
247  *
248  * DDR Autocalibration Method_B is the default.
249  */
250 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
251 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration */
252 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
253 #undef  CONFIG_PPC4xx_DDR_METHOD_A
254 #endif
255
256 #define CONFIG_SYS_SDRAM0_MB0CF_BASE    ((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
257
258 /* DDR1/2 SDRAM Device Control Register Data Values */
259 #define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3)    | \
260                                  SDRAM_RXBAS_SDSZ_256MB         | \
261                                  SDRAM_RXBAS_SDAM_MODE7         | \
262                                  SDRAM_RXBAS_SDBE_ENABLE)
263 #define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
264 #define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
265 #define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
266 #define CONFIG_SYS_SDRAM0_MCOPT1        (SDRAM_MCOPT1_PMU_OPEN          | \
267                                  SDRAM_MCOPT1_8_BANKS           | \
268                                  SDRAM_MCOPT1_DDR2_TYPE         | \
269                                  SDRAM_MCOPT1_QDEP              | \
270                                  SDRAM_MCOPT1_DCOO_DISABLED)
271 #define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
272 #define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
273                                  SDRAM_MODT_EB0R_ENABLE)
274 #define CONFIG_SYS_SDRAM0_MODT1 0x00000000
275 #define CONFIG_SYS_SDRAM0_CODT          (SDRAM_CODT_RK0R_ON             | \
276                                  SDRAM_CODT_CKLZ_36OHM          | \
277                                  SDRAM_CODT_DQS_1_8_V_DDR2      | \
278                                  SDRAM_CODT_IO_NMODE)
279 #define CONFIG_SYS_SDRAM0_RTR           SDRAM_RTR_RINT_ENCODE(1560)
280 #define CONFIG_SYS_SDRAM0_INITPLR0      (SDRAM_INITPLR_ENABLE                   | \
281                 SDRAM_INITPLR_IMWT_ENCODE(80)                           | \
282                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
283 #define CONFIG_SYS_SDRAM0_INITPLR1      (SDRAM_INITPLR_ENABLE                   | \
284                 SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
285                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
286                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
287                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
288 #define CONFIG_SYS_SDRAM0_INITPLR2      (SDRAM_INITPLR_ENABLE                   | \
289                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
290                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
291                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)                 | \
292                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
293 #define CONFIG_SYS_SDRAM0_INITPLR3      (SDRAM_INITPLR_ENABLE                   | \
294                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
295                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
296                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)                 | \
297                 SDRAM_INITPLR_IMA_ENCODE(0))
298 #define CONFIG_SYS_SDRAM0_INITPLR4      (SDRAM_INITPLR_ENABLE                   | \
299                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
300                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
301                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
302                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
303                                          JEDEC_MA_EMR_RTT_75OHM))
304 #define CONFIG_SYS_SDRAM0_INITPLR5      (SDRAM_INITPLR_ENABLE                   | \
305                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
306                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
307                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
308                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
309                                          JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
310                                          JEDEC_MA_MR_BLEN_4 | \
311                                          JEDEC_MA_MR_DLL_RESET))
312 #define CONFIG_SYS_SDRAM0_INITPLR6      (SDRAM_INITPLR_ENABLE                   | \
313                 SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
314                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
315                 SDRAM_INITPLR_IBA_ENCODE(0x0)                           | \
316                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
317 #define CONFIG_SYS_SDRAM0_INITPLR7      (SDRAM_INITPLR_ENABLE                   | \
318                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
319                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
320 #define CONFIG_SYS_SDRAM0_INITPLR8      (SDRAM_INITPLR_ENABLE                   | \
321                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
322                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
323 #define CONFIG_SYS_SDRAM0_INITPLR9      (SDRAM_INITPLR_ENABLE                   | \
324                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
325                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
326 #define CONFIG_SYS_SDRAM0_INITPLR10     (SDRAM_INITPLR_ENABLE                   | \
327                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
328                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
329 #define CONFIG_SYS_SDRAM0_INITPLR11     (SDRAM_INITPLR_ENABLE                   | \
330                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
331                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
332                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
333                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
334                                          JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
335                                          JEDEC_MA_MR_BLEN_4))
336 #define CONFIG_SYS_SDRAM0_INITPLR12     (SDRAM_INITPLR_ENABLE                   | \
337                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
338                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
339                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
340                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
341                                          JEDEC_MA_EMR_RDQS_DISABLE | \
342                                          JEDEC_MA_EMR_DQS_DISABLE | \
343                                          JEDEC_MA_EMR_RTT_DISABLED | \
344                                          JEDEC_MA_EMR_ODS_NORMAL))
345 #define CONFIG_SYS_SDRAM0_INITPLR13     (SDRAM_INITPLR_ENABLE                   | \
346                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
347                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
348                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
349                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
350                                          JEDEC_MA_EMR_RDQS_DISABLE | \
351                                          JEDEC_MA_EMR_DQS_DISABLE | \
352                                          JEDEC_MA_EMR_RTT_DISABLED | \
353                                          JEDEC_MA_EMR_ODS_NORMAL))
354 #define CONFIG_SYS_SDRAM0_INITPLR14     (SDRAM_INITPLR_DISABLE)
355 #define CONFIG_SYS_SDRAM0_INITPLR15     (SDRAM_INITPLR_DISABLE)
356 #define CONFIG_SYS_SDRAM0_RQDC          (SDRAM_RQDC_RQDE_ENABLE | \
357                                  SDRAM_RQDC_RQFD_ENCODE(56))
358 #define CONFIG_SYS_SDRAM0_RFDC          SDRAM_RFDC_RFFD_ENCODE(521)
359 #define CONFIG_SYS_SDRAM0_RDCC          (SDRAM_RDCC_RDSS_T2)
360 #define CONFIG_SYS_SDRAM0_DLCR          (SDRAM_DLCR_DCLM_AUTO           | \
361                                  SDRAM_DLCR_DLCS_CONT_DONE      | \
362                                  SDRAM_DLCR_DLCV_ENCODE(165))
363 #define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
364 #define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
365 #define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
366                                  SDRAM_SDTR1_RTW_2_CLK  | \
367                                  SDRAM_SDTR1_RTRO_1_CLK)
368 #define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK          | \
369                                  SDRAM_SDTR2_WTR_2_CLK          | \
370                                  SDRAM_SDTR2_XSNR_32_CLK        | \
371                                  SDRAM_SDTR2_WPC_4_CLK          | \
372                                  SDRAM_SDTR2_RPC_2_CLK          | \
373                                  SDRAM_SDTR2_RP_3_CLK           | \
374                                  SDRAM_SDTR2_RRD_2_CLK)
375 #define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8)      | \
376                                  SDRAM_SDTR3_RC_ENCODE(11)      | \
377                                  SDRAM_SDTR3_XCS                | \
378                                  SDRAM_SDTR3_RFC_ENCODE(26))
379 #define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
380                                  SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
381                                  SDRAM_MMODE_BLEN_4)
382 #define CONFIG_SYS_SDRAM0_MEMODE        (SDRAM_MEMODE_DQS_DISABLE | \
383                                  SDRAM_MEMODE_RTT_75OHM)
384
385 /*-----------------------------------------------------------------------
386  * I2C
387  *----------------------------------------------------------------------*/
388 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
389
390 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52    /* I2C boot EEPROM (24C02BN)    */
391 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address             */
392 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
393 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
394
395 /* I2C bootstrap EEPROM */
396 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
397 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
398 #define CONFIG_4xx_CONFIG_BLOCKSIZE             16
399
400 /* Standard DTT sensor configuration */
401 #define CONFIG_DTT_DS1775       1
402 #define CONFIG_DTT_SENSORS      { 0 }
403 #define CONFIG_SYS_I2C_DTT_ADDR 0x48
404
405 /* RTC configuration */
406 #define CONFIG_RTC_DS1338       1
407 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
408
409 /*-----------------------------------------------------------------------
410  * Ethernet
411  *----------------------------------------------------------------------*/
412 #define CONFIG_M88E1111_PHY     1
413 #define CONFIG_IBM_EMAC4_V4     1
414 #define CONFIG_EMAC_PHY_MODE    EMAC_PHY_MODE_RGMII_RGMII
415 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
416
417 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
418 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
419
420 #define CONFIG_HAS_ETH0         1
421
422 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
423 #define CONFIG_PHY1_ADDR        2
424
425 /* Debug messages for the DDR autocalibration */
426 #define CONFIG_AUTOCALIB                "silent\0"  /* default is non-verbose */
427
428 /*
429  * Default environment variables
430  */
431 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
432         CONFIG_AMCC_DEF_ENV                                             \
433         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
434         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
435         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
436         CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
437         "logversion=2\0"                                                \
438         "kernel_addr=fc000000\0"                                        \
439         "fdt_addr=fc1e0000\0"                                           \
440         "ramdisk_addr=fc200000\0"                                       \
441         "pciconfighost=1\0"                                             \
442         "pcie_mode=RP:RP\0"                                             \
443         ""
444
445 /*
446  * Commands additional to the ones defined in amcc-common.h
447  */
448 #define CONFIG_CMD_CHIP_CONFIG
449 #define CONFIG_CMD_DATE
450 #define CONFIG_CMD_LOG
451 #define CONFIG_CMD_NAND
452 #define CONFIG_CMD_PCI
453 #define CONFIG_CMD_SNTP
454
455 /*
456  * Don't run the memory POST on the NAND-booting version. It will
457  * overwrite part of the U-Boot image which is already loaded from NAND
458  * to SDRAM.
459  */
460 #if defined(CONFIG_NAND_U_BOOT)
461 #define CONFIG_SYS_POST_MEMORY_ON       0
462 #else
463 #define CONFIG_SYS_POST_MEMORY_ON       CONFIG_SYS_POST_MEMORY
464 #endif
465
466 /* POST support */
467 #define CONFIG_POST             (CONFIG_SYS_POST_CACHE          | \
468                                  CONFIG_SYS_POST_CPU            | \
469                                  CONFIG_SYS_POST_ETHER          | \
470                                  CONFIG_SYS_POST_I2C            | \
471                                  CONFIG_SYS_POST_MEMORY_ON      | \
472                                  CONFIG_SYS_POST_UART)
473
474 /* Define here the base-addresses of the UARTs to test in POST */
475 #define CONFIG_SYS_POST_UART_TABLE      { CONFIG_SYS_NS16550_COM1, \
476                         CONFIG_SYS_NS16550_COM2 }
477
478 #define CONFIG_LOGBUFFER
479 #define CONFIG_SYS_POST_CACHE_ADDR      0x00800000 /* free virtual address      */
480
481 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
482
483 /*-----------------------------------------------------------------------
484  * PCI stuff
485  *----------------------------------------------------------------------*/
486 #define CONFIG_PCI                      /* include pci support          */
487 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
488 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
489 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
490
491 /*-----------------------------------------------------------------------
492  * PCIe stuff
493  *----------------------------------------------------------------------*/
494 #define CONFIG_SYS_PCIE_MEMBASE 0x90000000      /* mapped PCIe memory   */
495 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* 128 Meg, smallest incr per port */
496
497 #define CONFIG_SYS_PCIE0_CFGBASE        0xa0000000      /* remote access */
498 #define CONFIG_SYS_PCIE0_XCFGBASE       0xb0000000      /* local access */
499 #define CONFIG_SYS_PCIE0_CFGMASK        0xe0000001      /* 512 Meg */
500
501 #define CONFIG_SYS_PCIE1_CFGBASE        0xc0000000      /* remote access */
502 #define CONFIG_SYS_PCIE1_XCFGBASE       0xd0000000      /* local access */
503 #define CONFIG_SYS_PCIE1_CFGMASK        0xe0000001      /* 512 Meg */
504
505 #define CONFIG_SYS_PCIE0_UTLBASE        0xef502000
506 #define CONFIG_SYS_PCIE1_UTLBASE        0xef503000
507
508 /* base address of inbound PCIe window */
509 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
510
511 /*-----------------------------------------------------------------------
512  * External Bus Controller (EBC) Setup
513  *----------------------------------------------------------------------*/
514 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
515 /* booting from NAND, so NAND chips select has to be on CS 0 */
516 #define CONFIG_SYS_NAND_CS              0               /* NAND chip connected to CSx   */
517
518 /* Memory Bank 1 (NOR-FLASH) initialization                                     */
519 #define CONFIG_SYS_EBC_PB1AP            0x05806500
520 #define CONFIG_SYS_EBC_PB1CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
521
522 /* Memory Bank 0 (NAND-FLASH) initialization                                    */
523 #define CONFIG_SYS_EBC_PB0AP            0x018003c0
524 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1e000)
525 #else
526 #define CONFIG_SYS_NAND_CS              1               /* NAND chip connected to CSx   */
527
528 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
529 #define CONFIG_SYS_EBC_PB0AP            0x05806500
530 #define CONFIG_SYS_EBC_PB0CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
531
532 /* Memory Bank 1 (NAND-FLASH) initialization                                    */
533 #define CONFIG_SYS_EBC_PB1AP            0x018003c0
534 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_NAND_ADDR | 0x1e000)
535 #endif
536
537 /* Memory Bank 2 (FPGA) initialization                                  */
538 #define CONFIG_SYS_EBC_PB2AP            (EBC_BXAP_BME_ENABLED |         \
539                                          EBC_BXAP_FWT_ENCODE(6) |       \
540                                          EBC_BXAP_BWT_ENCODE(1) |       \
541                                          EBC_BXAP_BCE_DISABLE |         \
542                                          EBC_BXAP_BCT_2TRANS |          \
543                                          EBC_BXAP_CSN_ENCODE(0) |       \
544                                          EBC_BXAP_OEN_ENCODE(0) |       \
545                                          EBC_BXAP_WBN_ENCODE(3) |       \
546                                          EBC_BXAP_WBF_ENCODE(1) |       \
547                                          EBC_BXAP_TH_ENCODE(4) |        \
548                                          EBC_BXAP_RE_DISABLED |         \
549                                          EBC_BXAP_SOR_DELAYED |         \
550                                          EBC_BXAP_BEM_WRITEONLY |       \
551                                          EBC_BXAP_PEN_DISABLED)
552 #define CONFIG_SYS_EBC_PB2CR    (CONFIG_SYS_FPGA_BASE | 0x18000)
553
554 #define CONFIG_SYS_EBC_CFG              0x7FC00000 /*  EBC0_CFG */
555
556 /*-----------------------------------------------------------------------
557  * GPIO Setup
558  *----------------------------------------------------------------------*/
559 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
560 {                                                                                       \
561 /* GPIO Core 0 */                                                                       \
562 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0)                 */      \
563 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1)                 */      \
564 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2)                 */      \
565 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3)                 */      \
566 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20)    USB2_DATA(4)    */      \
567 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21)    USB2_DATA(5)    */      \
568 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22)    USB2_DATA(6)    */      \
569 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23)    USB2_DATA(7)    */      \
570 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1)   IRQ(7)          */      \
571 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2)   IRQ(8)          */      \
572 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)  IRQ(9)          */      \
573 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6)                         */      \
574 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)   USB2_DATA(0)    */      \
575 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)   USB2_DATA(1)    */      \
576 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)   USB2_DATA(2)    */      \
577 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)   USB2_DATA(3)    */      \
578 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD      UART1_CTS       */      \
579 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR      UART1_RTS       */      \
580 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS                      */      \
581 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS                      */      \
582 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR      UART1_TX        */      \
583 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI       UART1_RX        */      \
584 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ   DMA_ACK2        */      \
585 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK   DMA_REQ2        */      \
586 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ    DMA_EOT2        IRQ(4) */ \
587 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK    DMA_ACK3        IRQ(3) */ \
588 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)    DMA_EOT0        TS(3) */ \
589 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ    DMA_EOT3        IRQ(5) */ \
590 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO28                                */      \
591 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1       IRQ(2)          */      \
592 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1       IRQ(1)          */      \
593 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO31 DMA_ACK1       IRQ(0)          */      \
594 }                                                                                               \
595 }
596
597 /*-----------------------------------------------------------------------
598  * Some Kilauea stuff..., mainly fpga registers
599  */
600 #define CONFIG_SYS_FPGA_REG_BASE                CONFIG_SYS_FPGA_BASE
601 #define CONFIG_SYS_FPGA_FIFO_BASE               (CONFIG_SYS_FPGA_BASE | (1 << 10))
602
603 /* interrupt */
604 #define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT       0x80000000
605 #define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT       0x40000000
606 #define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT       0x20000000
607 #define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT       0x10000000
608 #define CONFIG_SYS_FPGA_PHY0_INT                0x08000000
609 #define CONFIG_SYS_FPGA_PHY1_INT                0x04000000
610 #define CONFIG_SYS_FPGA_SLIC0_INT               0x02000000
611 #define CONFIG_SYS_FPGA_SLIC1_INT               0x01000000
612
613 /* DPRAM setting */
614 /* 00: 32B; 01: 64B; 10: 128B; 11: 256B  */
615 #define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE        0x00400000      /* 64 B */
616 #define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE        0x00100000      /* 64 B */
617 #define CONFIG_SYS_FPGA_DPRAM_RW_TYPE           0x00080000
618 #define CONFIG_SYS_FPGA_DPRAM_RST               0x00040000
619 #define CONFIG_SYS_FPGA_UART0_FO                0x00020000
620 #define CONFIG_SYS_FPGA_UART1_FO                0x00010000
621
622 /* loopback */
623 #define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK       0x00004000
624 #define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK       0x00008000
625 #define CONFIG_SYS_FPGA_SLIC0_ENABLE            0x00002000
626 #define CONFIG_SYS_FPGA_SLIC1_ENABLE            0x00001000
627 #define CONFIG_SYS_FPGA_SLIC0_CS                0x00000800
628 #define CONFIG_SYS_FPGA_SLIC1_CS                0x00000400
629 #define CONFIG_SYS_FPGA_USER_LED0               0x00000200
630 #define CONFIG_SYS_FPGA_USER_LED1               0x00000100
631
632 #define CONFIG_SYS_FPGA_MAGIC_MASK              0xffff0000
633 #define CONFIG_SYS_FPGA_MAGIC                   0xabcd0000
634 #define CONFIG_SYS_FPGA_VER_MASK                0x0000ff00
635
636 #endif  /* __CONFIG_H */