Merge branch 'next' of git://git.denx.de/u-boot-video
[platform/kernel/u-boot.git] / include / configs / katmai.h
1 /*
2  * (C) Copyright 2007
3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
4  *
5  * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25
26 /************************************************************************
27  * katmai.h - configuration for AMCC Katmai (440SPe)
28  ***********************************************************************/
29
30 #ifndef __CONFIG_H
31 #define __CONFIG_H
32
33 /*-----------------------------------------------------------------------
34  * High Level Configuration Options
35  *----------------------------------------------------------------------*/
36 #define CONFIG_KATMAI                   1       /* Board is Katmai      */
37 #define CONFIG_4xx                      1       /* ... PPC4xx family    */
38 #define CONFIG_440                      1       /* ... PPC440 family    */
39 #define CONFIG_440SPE                   1       /* Specifc SPe support  */
40 #define CONFIG_440SPE_REVA              1       /* Support old Rev A.   */
41 #define CONFIG_SYS_CLK_FREQ     33333333        /* external freq to pll */
42 #define CONFIG_SYS_4xx_RESET_TYPE       0x2     /* use chip reset on this board */
43
44 /*
45  * Enable this board for more than 2GB of SDRAM
46  */
47 #define CONFIG_PHYS_64BIT
48 #define CONFIG_VERY_BIG_RAM
49
50 /*
51  * Include common defines/options for all AMCC eval boards
52  */
53 #define CONFIG_HOSTNAME         katmai
54 #include "amcc-common.h"
55
56 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_pre_init          */
57 #undef  CONFIG_SHOW_BOOT_PROGRESS
58
59 /*-----------------------------------------------------------------------
60  * Base addresses -- Note these are effective addresses where the
61  * actual resources get mapped (not physical addresses)
62  *----------------------------------------------------------------------*/
63 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH       */
64 #define CONFIG_SYS_ISRAM_BASE           0x90000000      /* internal SRAM        */
65
66 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory    */
67 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
68 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
69
70 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
71 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* smallest incr for PCIe port */
72 #define CONFIG_SYS_PCIE_BASE            0xe0000000      /* PCIe UTL regs */
73
74 #define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
75 #define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
76 #define CONFIG_SYS_PCIE2_CFGBASE        0xc2000000
77 #define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
78 #define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
79 #define CONFIG_SYS_PCIE2_XCFGBASE       0xc3002000
80
81 /* base address of inbound PCIe window */
82 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
83
84 /* System RAM mapped to PCI space */
85 #define CONFIG_PCI_SYS_MEM_BUS  CONFIG_SYS_SDRAM_BASE
86 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
87 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
88
89 #define CONFIG_SYS_ACE_BASE             0xfe000000      /* Xilinx ACE controller - Compact Flash */
90
91 /*-----------------------------------------------------------------------
92  * Initial RAM & stack pointer (placed in internal SRAM)
93  *----------------------------------------------------------------------*/
94 #define CONFIG_SYS_TEMP_STACK_OCM       1
95 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_ISRAM_BASE
96 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_ISRAM_BASE   /* Initial RAM address  */
97 #define CONFIG_SYS_INIT_RAM_END 0x2000          /* End of used area in RAM */
98 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
99
100 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
101 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
102
103 /*-----------------------------------------------------------------------
104  * Serial Port
105  *----------------------------------------------------------------------*/
106 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
107 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
108
109 /*-----------------------------------------------------------------------
110  * DDR SDRAM
111  *----------------------------------------------------------------------*/
112 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
113 #define SPD_EEPROM_ADDRESS      {0x51, 0x52}    /* SPD i2c spd addresses*/
114 #define CONFIG_DDR_ECC          1       /* with ECC support             */
115 #define CONFIG_DDR_RQDC_FIXED   0x80000038 /* optimal value found by GDA*/
116 #undef  CONFIG_STRESS
117
118 /*-----------------------------------------------------------------------
119  * I2C
120  *----------------------------------------------------------------------*/
121 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address  */
122
123 #define CONFIG_I2C_MULTI_BUS
124 #define CONFIG_SYS_SPD_BUS_NUM          0       /* The I2C bus for SPD          */
125
126 #define IIC0_BOOTPROM_ADDR      0x50
127 #define IIC0_ALT_BOOTPROM_ADDR  0x54
128
129 #define CONFIG_SYS_I2C_MULTI_EEPROMS
130 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0x50)
131 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
132 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
133 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
134
135 /* I2C bootstrap EEPROM */
136 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x50
137 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
138 #define CONFIG_4xx_CONFIG_BLOCKSIZE             8
139
140 /* I2C RTC */
141 #define CONFIG_RTC_M41T11       1
142 #define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC          */
143 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
144 #define CONFIG_SYS_M41T11_BASE_YEAR     1900    /* play along with linux        */
145
146 /* I2C DTT */
147 #define CONFIG_DTT_ADM1021      1       /* ADM1021 temp sensor support  */
148 #define CONFIG_SYS_DTT_BUS_NUM          1       /* The I2C bus for DTT          */
149 /*
150  * standard dtt sensor configuration - bottom bit will determine local or
151  * remote sensor of the ADM1021, the rest determines index into
152  * CONFIG_SYS_DTT_ADM1021 array below.
153  */
154 #define CONFIG_DTT_SENSORS      { 0, 1 }
155
156 /*
157  * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
158  * there will be one entry in this array for each two (dummy) sensors in
159  * CONFIG_DTT_SENSORS.
160  *
161  * For Katmai board:
162  * - only one ADM1021
163  * - i2c addr 0x18
164  * - conversion rate 0x02 = 0.25 conversions/second
165  * - ALERT ouput disabled
166  * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
167  * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
168  */
169 #define CONFIG_SYS_DTT_ADM1021          { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
170
171 /*-----------------------------------------------------------------------
172  * Environment
173  *----------------------------------------------------------------------*/
174 #define CONFIG_ENV_IS_IN_FLASH  1       /* Environment uses flash       */
175
176 /*
177  * Default environment variables
178  */
179 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
180         CONFIG_AMCC_DEF_ENV                                             \
181         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
182         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
183         "kernel_addr=ff000000\0"                                        \
184         "fdt_addr=ff1e0000\0"                                           \
185         "ramdisk_addr=ff200000\0"                                       \
186         "pciconfighost=1\0"                                             \
187         "pcie_mode=RP:RP:RP\0"                                          \
188         ""
189
190 /*
191  * Commands additional to the ones defined in amcc-common.h
192  */
193 #define CONFIG_CMD_CHIP_CONFIG
194 #define CONFIG_CMD_DATE
195 #define CONFIG_CMD_ECCTEST
196 #define CONFIG_CMD_EXT2
197 #define CONFIG_CMD_FAT
198 #define CONFIG_CMD_PCI
199 #define CONFIG_CMD_SDRAM
200 #define CONFIG_CMD_SNTP
201
202 #define CONFIG_IBM_EMAC4_V4     1       /* 440SPe has this EMAC version */
203 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
204 #define CONFIG_HAS_ETH0
205 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
206 #define CONFIG_PHY_RESET_DELAY  1000
207 #define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
208 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
209
210 /*-----------------------------------------------------------------------
211  * FLASH related
212  *----------------------------------------------------------------------*/
213 #define CONFIG_SYS_FLASH_CFI
214 #define CONFIG_FLASH_CFI_DRIVER
215 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
216 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
217
218 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
219 #define CONFIG_SYS_MAX_FLASH_BANKS     1                    /* number of banks      */
220 #define CONFIG_SYS_MAX_FLASH_SECT       1024                /* sectors per device   */
221
222 #undef  CONFIG_SYS_FLASH_CHECKSUM
223 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
224 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
225
226 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
227 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
228 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
229
230 /* Address and size of Redundant Environment Sector     */
231 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
232 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
233
234 /*-----------------------------------------------------------------------
235  * PCI stuff
236  *-----------------------------------------------------------------------
237  */
238 /* General PCI */
239 #define CONFIG_PCI                      /* include pci support          */
240 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
241 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
242 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
243
244 /* Board-specific PCI */
245 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
246 #undef  CONFIG_SYS_PCI_MASTER_INIT
247
248 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                          */
249 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever                     */
250 /* #define CONFIG_SYS_PCI_SUBSYS_ID     CONFIG_SYS_PCI_SUBSYS_DEVICEID */
251
252 /*
253  *  NETWORK Support (PCI):
254  */
255 /* Support for Intel 82557/82559/82559ER chips. */
256 #define CONFIG_EEPRO100
257
258 /*-----------------------------------------------------------------------
259  * Xilinx System ACE support
260  *----------------------------------------------------------------------*/
261 #define CONFIG_SYSTEMACE        1       /* Enable SystemACE support     */
262 #define CONFIG_SYS_SYSTEMACE_WIDTH      16      /* Data bus width is 16         */
263 #define CONFIG_SYS_SYSTEMACE_BASE       CONFIG_SYS_ACE_BASE
264 #define CONFIG_DOS_PARTITION    1
265
266 /*-----------------------------------------------------------------------
267  * External Bus Controller (EBC) Setup
268  *----------------------------------------------------------------------*/
269
270 /* Memory Bank 0 (Flash) initialization                                 */
271 #define CONFIG_SYS_EBC_PB0AP            (EBC_BXAP_BME_DISABLED      |           \
272                                  EBC_BXAP_TWT_ENCODE(7)     |           \
273                                  EBC_BXAP_BCE_DISABLE       |           \
274                                  EBC_BXAP_BCT_2TRANS        |           \
275                                  EBC_BXAP_CSN_ENCODE(0)     |           \
276                                  EBC_BXAP_OEN_ENCODE(0)     |           \
277                                  EBC_BXAP_WBN_ENCODE(0)     |           \
278                                  EBC_BXAP_WBF_ENCODE(0)     |           \
279                                  EBC_BXAP_TH_ENCODE(0)      |           \
280                                  EBC_BXAP_RE_DISABLED       |           \
281                                  EBC_BXAP_SOR_DELAYED       |           \
282                                  EBC_BXAP_BEM_WRITEONLY     |           \
283                                  EBC_BXAP_PEN_DISABLED)
284 #define CONFIG_SYS_EBC_PB0CR            (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |   \
285                                  EBC_BXCR_BS_16MB                    |  \
286                                  EBC_BXCR_BU_RW                      |  \
287                                  EBC_BXCR_BW_16BIT)
288
289 /* Memory Bank 1 (Xilinx System ACE controller) initialization          */
290 #define CONFIG_SYS_EBC_PB1AP            (EBC_BXAP_BME_DISABLED      |           \
291                                  EBC_BXAP_TWT_ENCODE(4)     |           \
292                                  EBC_BXAP_BCE_DISABLE       |           \
293                                  EBC_BXAP_BCT_2TRANS        |           \
294                                  EBC_BXAP_CSN_ENCODE(0)     |           \
295                                  EBC_BXAP_OEN_ENCODE(0)     |           \
296                                  EBC_BXAP_WBN_ENCODE(0)     |           \
297                                  EBC_BXAP_WBF_ENCODE(0)     |           \
298                                  EBC_BXAP_TH_ENCODE(0)      |           \
299                                  EBC_BXAP_RE_DISABLED       |           \
300                                  EBC_BXAP_SOR_NONDELAYED    |           \
301                                  EBC_BXAP_BEM_WRITEONLY     |           \
302                                  EBC_BXAP_PEN_DISABLED)
303 #define CONFIG_SYS_EBC_PB1CR            (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE)  |    \
304                                  EBC_BXCR_BS_1MB                    |   \
305                                  EBC_BXCR_BU_RW                     |   \
306                                  EBC_BXCR_BW_16BIT)
307
308 /*-------------------------------------------------------------------------
309  * Initialize EBC CONFIG -
310  * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
311  * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
312  *-------------------------------------------------------------------------*/
313 #define CONFIG_SYS_EBC_CFG              (EBC_CFG_LE_UNLOCK    | \
314                                  EBC_CFG_PTD_ENABLE   | \
315                                  EBC_CFG_RTC_16PERCLK | \
316                                  EBC_CFG_ATC_PREVIOUS | \
317                                  EBC_CFG_DTC_PREVIOUS | \
318                                  EBC_CFG_CTC_PREVIOUS | \
319                                  EBC_CFG_OEO_PREVIOUS | \
320                                  EBC_CFG_EMC_DEFAULT  | \
321                                  EBC_CFG_PME_DISABLE  | \
322                                  EBC_CFG_PR_16)
323
324 /*-----------------------------------------------------------------------
325  * GPIO Setup
326  *----------------------------------------------------------------------*/
327 #define CONFIG_SYS_GPIO_PCIE_PRESENT0   17
328 #define CONFIG_SYS_GPIO_PCIE_PRESENT1   21
329 #define CONFIG_SYS_GPIO_PCIE_PRESENT2   23
330 #define CONFIG_SYS_GPIO_RS232_FORCEOFF  30
331
332 #define CONFIG_SYS_PFC0         (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
333                                  GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
334                                  GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
335                                  GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
336 #define CONFIG_SYS_GPIO_OR              GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
337 #define CONFIG_SYS_GPIO_TCR             GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
338 #define CONFIG_SYS_GPIO_ODR             0
339
340 #endif  /* __CONFIG_H */