include/configs/katmai.h

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /************************************************************************
  11  * katmai.h - configuration for AMCC Katmai (440SPe)
  12  ***********************************************************************/
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 /*-----------------------------------------------------------------------
  18  * High Level Configuration Options
  19  *----------------------------------------------------------------------*/
  20 #define CONFIG_KATMAI                   1       /* Board is Katmai      */
  21 #define CONFIG_440                      1       /* ... PPC440 family    */
  22 #define CONFIG_440SPE                   1       /* Specifc SPe support  */
  23 #define CONFIG_440SPE_REVA              1       /* Support old Rev A.   */
  24 #define CONFIG_SYS_CLK_FREQ     33333333        /* external freq to pll */
  25 #define CONFIG_SYS_4xx_RESET_TYPE       0x2     /* use chip reset on this board */
  26
  27 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  28
  29 /*
  30  * Enable this board for more than 2GB of SDRAM
  31  */
  32 #define CONFIG_VERY_BIG_RAM
  33
  34 /*
  35  * Include common defines/options for all AMCC eval boards
  36  */
  37 #define CONFIG_HOSTNAME         katmai
  38 #include "amcc-common.h"
  39
  40 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_pre_init          */
  41 #undef  CONFIG_SHOW_BOOT_PROGRESS
  42
  43 /*-----------------------------------------------------------------------
  44  * Base addresses -- Note these are effective addresses where the
  45  * actual resources get mapped (not physical addresses)
  46  *----------------------------------------------------------------------*/
  47 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH       */
  48 #define CONFIG_SYS_ISRAM_BASE           0x90000000      /* internal SRAM        */
  49
  50 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory    */
  51 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
  52 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  53
  54 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
  55 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* smallest incr for PCIe port */
  56 #define CONFIG_SYS_PCIE_BASE            0xe0000000      /* PCIe UTL regs */
  57
  58 #define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
  59 #define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
  60 #define CONFIG_SYS_PCIE2_CFGBASE        0xc2000000
  61 #define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
  62 #define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
  63 #define CONFIG_SYS_PCIE2_XCFGBASE       0xc3002000
  64
  65 /* base address of inbound PCIe window */
  66 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
  67
  68 /* System RAM mapped to PCI space */
  69 #define CONFIG_PCI_SYS_MEM_BUS  CONFIG_SYS_SDRAM_BASE
  70 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
  71 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
  72
  73 #define CONFIG_SYS_ACE_BASE             0xfe000000      /* Xilinx ACE controller - Compact Flash */
  74
  75 /*-----------------------------------------------------------------------
  76  * Initial RAM & stack pointer (placed in internal SRAM)
  77  *----------------------------------------------------------------------*/
  78 #define CONFIG_SYS_TEMP_STACK_OCM       1
  79 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_ISRAM_BASE
  80 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_ISRAM_BASE   /* Initial RAM address  */
  81 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000          /* Size of used area in RAM */
  82
  83 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  84 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  85
  86 /*-----------------------------------------------------------------------
  87  * Serial Port
  88  *----------------------------------------------------------------------*/
  89 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  90 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
  91
  92 /*-----------------------------------------------------------------------
  93  * DDR SDRAM
  94  *----------------------------------------------------------------------*/
  95 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
  96 #define SPD_EEPROM_ADDRESS      {0x51, 0x52}    /* SPD i2c spd addresses*/
  97 #define CONFIG_DDR_ECC          1       /* with ECC support             */
  98 #define CONFIG_DDR_RQDC_FIXED   0x80000038 /* optimal value found by GDA*/
  99 #undef  CONFIG_STRESS
 100
 101 /*-----------------------------------------------------------------------
 102  * I2C
 103  *----------------------------------------------------------------------*/
 104 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
 105
 106 #define CONFIG_SYS_SPD_BUS_NUM          0       /* The I2C bus for SPD          */
 107
 108 #define IIC0_BOOTPROM_ADDR      0x50
 109 #define IIC0_ALT_BOOTPROM_ADDR  0x54
 110
 111 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0x50)
 112 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 113 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 114 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 115
 116 /* I2C bootstrap EEPROM */
 117 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x50
 118 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 119 #define CONFIG_4xx_CONFIG_BLOCKSIZE             8
 120
 121 /* I2C RTC */
 122 #define CONFIG_RTC_M41T11       1
 123 #define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC          */
 124 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 125 #define CONFIG_SYS_M41T11_BASE_YEAR     1900    /* play along with linux        */
 126
 127 /* I2C DTT */
 128 #define CONFIG_DTT_ADM1021      1       /* ADM1021 temp sensor support  */
 129 #define CONFIG_SYS_DTT_BUS_NUM          1       /* The I2C bus for DTT          */
 130 /*
 131  * standard dtt sensor configuration - bottom bit will determine local or
 132  * remote sensor of the ADM1021, the rest determines index into
 133  * CONFIG_SYS_DTT_ADM1021 array below.
 134  */
 135 #define CONFIG_DTT_SENSORS      { 0, 1 }
 136
 137 /*
 138  * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
 139  * there will be one entry in this array for each two (dummy) sensors in
 140  * CONFIG_DTT_SENSORS.
 141  *
 142  * For Katmai board:
 143  * - only one ADM1021
 144  * - i2c addr 0x18
 145  * - conversion rate 0x02 = 0.25 conversions/second
 146  * - ALERT ouput disabled
 147  * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
 148  * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
 149  */
 150 #define CONFIG_SYS_DTT_ADM1021          { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
 151
 152 /*-----------------------------------------------------------------------
 153  * Environment
 154  *----------------------------------------------------------------------*/
 155 #define CONFIG_ENV_IS_IN_FLASH  1       /* Environment uses flash       */
 156
 157 /*
 158  * Default environment variables
 159  */
 160 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 161         CONFIG_AMCC_DEF_ENV                                             \
 162         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 163         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 164         "kernel_addr=ff000000\0"                                        \
 165         "fdt_addr=ff1e0000\0"                                           \
 166         "ramdisk_addr=ff200000\0"                                       \
 167         "pciconfighost=1\0"                                             \
 168         "pcie_mode=RP:RP:RP\0"                                          \
 169         ""
 170
 171 /*
 172  * Commands additional to the ones defined in amcc-common.h
 173  */
 174 #define CONFIG_CMD_CHIP_CONFIG
 175 #define CONFIG_CMD_DATE
 176 #define CONFIG_CMD_ECCTEST
 177 #define CONFIG_CMD_PCI
 178 #define CONFIG_CMD_SDRAM
 179
 180 #define CONFIG_IBM_EMAC4_V4     1       /* 440SPe has this EMAC version */
 181 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 182 #define CONFIG_HAS_ETH0
 183 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 184 #define CONFIG_PHY_RESET_DELAY  1000
 185 #define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
 186 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 187
 188 /*-----------------------------------------------------------------------
 189  * FLASH related
 190  *----------------------------------------------------------------------*/
 191 #define CONFIG_SYS_FLASH_CFI
 192 #define CONFIG_FLASH_CFI_DRIVER
 193 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 194 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 195
 196 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 197 #define CONFIG_SYS_MAX_FLASH_BANKS     1                    /* number of banks      */
 198 #define CONFIG_SYS_MAX_FLASH_SECT       1024                /* sectors per device   */
 199
 200 #undef  CONFIG_SYS_FLASH_CHECKSUM
 201 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 202 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 203
 204 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
 205 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 206 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 207
 208 /* Address and size of Redundant Environment Sector     */
 209 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 210 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 211
 212 /*-----------------------------------------------------------------------
 213  * PCI stuff
 214  *-----------------------------------------------------------------------
 215  */
 216 /* General PCI */
 217 #define CONFIG_PCI                      /* include pci support          */
 218 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 219 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
 220 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 221 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 222
 223 /* Board-specific PCI */
 224 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 225 #undef  CONFIG_SYS_PCI_MASTER_INIT
 226
 227 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                          */
 228 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever                     */
 229 /* #define CONFIG_SYS_PCI_SUBSYS_ID     CONFIG_SYS_PCI_SUBSYS_DEVICEID */
 230
 231 /*
 232  *  NETWORK Support (PCI):
 233  */
 234 /* Support for Intel 82557/82559/82559ER chips. */
 235 #define CONFIG_EEPRO100
 236
 237 /*-----------------------------------------------------------------------
 238  * Xilinx System ACE support
 239  *----------------------------------------------------------------------*/
 240 #define CONFIG_SYSTEMACE        1       /* Enable SystemACE support     */
 241 #define CONFIG_SYS_SYSTEMACE_WIDTH      16      /* Data bus width is 16         */
 242 #define CONFIG_SYS_SYSTEMACE_BASE       CONFIG_SYS_ACE_BASE
 243 #define CONFIG_DOS_PARTITION    1
 244
 245 /*-----------------------------------------------------------------------
 246  * External Bus Controller (EBC) Setup
 247  *----------------------------------------------------------------------*/
 248
 249 /* Memory Bank 0 (Flash) initialization                                 */
 250 #define CONFIG_SYS_EBC_PB0AP            (EBC_BXAP_BME_DISABLED      |           \
 251                                  EBC_BXAP_TWT_ENCODE(7)     |           \
 252                                  EBC_BXAP_BCE_DISABLE       |           \
 253                                  EBC_BXAP_BCT_2TRANS        |           \
 254                                  EBC_BXAP_CSN_ENCODE(0)     |           \
 255                                  EBC_BXAP_OEN_ENCODE(0)     |           \
 256                                  EBC_BXAP_WBN_ENCODE(0)     |           \
 257                                  EBC_BXAP_WBF_ENCODE(0)     |           \
 258                                  EBC_BXAP_TH_ENCODE(0)      |           \
 259                                  EBC_BXAP_RE_DISABLED       |           \
 260                                  EBC_BXAP_SOR_DELAYED       |           \
 261                                  EBC_BXAP_BEM_WRITEONLY     |           \
 262                                  EBC_BXAP_PEN_DISABLED)
 263 #define CONFIG_SYS_EBC_PB0CR            (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |   \
 264                                  EBC_BXCR_BS_16MB                    |  \
 265                                  EBC_BXCR_BU_RW                      |  \
 266                                  EBC_BXCR_BW_16BIT)
 267
 268 /* Memory Bank 1 (Xilinx System ACE controller) initialization          */
 269 #define CONFIG_SYS_EBC_PB1AP            (EBC_BXAP_BME_DISABLED      |           \
 270                                  EBC_BXAP_TWT_ENCODE(4)     |           \
 271                                  EBC_BXAP_BCE_DISABLE       |           \
 272                                  EBC_BXAP_BCT_2TRANS        |           \
 273                                  EBC_BXAP_CSN_ENCODE(0)     |           \
 274                                  EBC_BXAP_OEN_ENCODE(0)     |           \
 275                                  EBC_BXAP_WBN_ENCODE(0)     |           \
 276                                  EBC_BXAP_WBF_ENCODE(0)     |           \
 277                                  EBC_BXAP_TH_ENCODE(0)      |           \
 278                                  EBC_BXAP_RE_DISABLED       |           \
 279                                  EBC_BXAP_SOR_NONDELAYED    |           \
 280                                  EBC_BXAP_BEM_WRITEONLY     |           \
 281                                  EBC_BXAP_PEN_DISABLED)
 282 #define CONFIG_SYS_EBC_PB1CR            (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE)  |    \
 283                                  EBC_BXCR_BS_1MB                    |   \
 284                                  EBC_BXCR_BU_RW                     |   \
 285                                  EBC_BXCR_BW_16BIT)
 286
 287 /*-------------------------------------------------------------------------
 288  * Initialize EBC CONFIG -
 289  * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
 290  * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
 291  *-------------------------------------------------------------------------*/
 292 #define CONFIG_SYS_EBC_CFG              (EBC_CFG_LE_UNLOCK    | \
 293                                  EBC_CFG_PTD_ENABLE   | \
 294                                  EBC_CFG_RTC_16PERCLK | \
 295                                  EBC_CFG_ATC_PREVIOUS | \
 296                                  EBC_CFG_DTC_PREVIOUS | \
 297                                  EBC_CFG_CTC_PREVIOUS | \
 298                                  EBC_CFG_OEO_PREVIOUS | \
 299                                  EBC_CFG_EMC_DEFAULT  | \
 300                                  EBC_CFG_PME_DISABLE  | \
 301                                  EBC_CFG_PR_16)
 302
 303 /*-----------------------------------------------------------------------
 304  * GPIO Setup
 305  *----------------------------------------------------------------------*/
 306 #define CONFIG_SYS_GPIO_PCIE_PRESENT0   17
 307 #define CONFIG_SYS_GPIO_PCIE_PRESENT1   21
 308 #define CONFIG_SYS_GPIO_PCIE_PRESENT2   23
 309 #define CONFIG_SYS_GPIO_RS232_FORCEOFF  30
 310
 311 #define CONFIG_SYS_PFC0         (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
 312                                  GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
 313                                  GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
 314                                  GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
 315 #define CONFIG_SYS_GPIO_OR              GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
 316 #define CONFIG_SYS_GPIO_TCR             GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
 317 #define CONFIG_SYS_GPIO_ODR             0
 318
 319 #endif  /* __CONFIG_H */