3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 /************************************************************************
11 * katmai.h - configuration for AMCC Katmai (440SPe)
12 ***********************************************************************/
17 /*-----------------------------------------------------------------------
18 * High Level Configuration Options
19 *----------------------------------------------------------------------*/
20 #define CONFIG_KATMAI 1 /* Board is Katmai */
21 #define CONFIG_440 1 /* ... PPC440 family */
22 #define CONFIG_440SPE 1 /* Specifc SPe support */
23 #define CONFIG_440SPE_REVA 1 /* Support old Rev A. */
24 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
25 #define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
27 #define CONFIG_SYS_TEXT_BASE 0xFFFA0000
30 * Enable this board for more than 2GB of SDRAM
32 #define CONFIG_VERY_BIG_RAM
35 * Include common defines/options for all AMCC eval boards
37 #define CONFIG_HOSTNAME katmai
38 #include "amcc-common.h"
40 #undef CONFIG_SHOW_BOOT_PROGRESS
42 /*-----------------------------------------------------------------------
43 * Base addresses -- Note these are effective addresses where the
44 * actual resources get mapped (not physical addresses)
45 *----------------------------------------------------------------------*/
46 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
47 #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
49 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
50 #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
51 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
53 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
54 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
55 #define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
57 #define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
58 #define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
59 #define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000
60 #define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
61 #define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
62 #define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000
64 /* base address of inbound PCIe window */
65 #define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
67 /* System RAM mapped to PCI space */
68 #define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
69 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
70 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
72 #define CONFIG_SYS_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */
74 /*-----------------------------------------------------------------------
75 * Initial RAM & stack pointer (placed in internal SRAM)
76 *----------------------------------------------------------------------*/
77 #define CONFIG_SYS_TEMP_STACK_OCM 1
78 #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
79 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
80 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
82 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
83 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
85 /*-----------------------------------------------------------------------
87 *----------------------------------------------------------------------*/
88 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
89 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
91 /*-----------------------------------------------------------------------
93 *----------------------------------------------------------------------*/
94 #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
95 #define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/
96 #define CONFIG_DDR_ECC 1 /* with ECC support */
97 #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* optimal value found by GDA*/
100 /*-----------------------------------------------------------------------
102 *----------------------------------------------------------------------*/
103 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
105 #define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */
107 #define IIC0_BOOTPROM_ADDR 0x50
108 #define IIC0_ALT_BOOTPROM_ADDR 0x54
110 #define CONFIG_SYS_I2C_EEPROM_ADDR (0x50)
111 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
112 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
113 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
115 /* I2C bootstrap EEPROM */
116 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
117 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
118 #define CONFIG_4xx_CONFIG_BLOCKSIZE 8
121 #define CONFIG_RTC_M41T11 1
122 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
123 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
124 #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
126 /*-----------------------------------------------------------------------
128 *----------------------------------------------------------------------*/
129 #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
132 * Default environment variables
134 #define CONFIG_EXTRA_ENV_SETTINGS \
135 CONFIG_AMCC_DEF_ENV \
136 CONFIG_AMCC_DEF_ENV_POWERPC \
137 CONFIG_AMCC_DEF_ENV_NOR_UPD \
138 "kernel_addr=ff000000\0" \
139 "fdt_addr=ff1e0000\0" \
140 "ramdisk_addr=ff200000\0" \
141 "pciconfighost=1\0" \
142 "pcie_mode=RP:RP:RP\0" \
146 * Commands additional to the ones defined in amcc-common.h
148 #define CONFIG_CMD_ECCTEST
149 #define CONFIG_CMD_PCI
150 #define CONFIG_CMD_SDRAM
152 #define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */
153 #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
154 #define CONFIG_HAS_ETH0
155 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
156 #define CONFIG_PHY_RESET_DELAY 1000
157 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
158 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
160 /*-----------------------------------------------------------------------
162 *----------------------------------------------------------------------*/
163 #define CONFIG_SYS_FLASH_CFI
164 #define CONFIG_FLASH_CFI_DRIVER
165 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
166 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
168 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
169 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
170 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
172 #undef CONFIG_SYS_FLASH_CHECKSUM
173 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
174 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
176 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
177 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
178 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
180 /* Address and size of Redundant Environment Sector */
181 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
182 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
184 /*-----------------------------------------------------------------------
186 *-----------------------------------------------------------------------
189 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
190 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
191 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
193 /* Board-specific PCI */
194 #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
195 #undef CONFIG_SYS_PCI_MASTER_INIT
197 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
198 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
199 /* #define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_DEVICEID */
202 * NETWORK Support (PCI):
204 /* Support for Intel 82557/82559/82559ER chips. */
205 #define CONFIG_EEPRO100
207 /*-----------------------------------------------------------------------
208 * Xilinx System ACE support
209 *----------------------------------------------------------------------*/
210 #define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */
211 #define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
212 #define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE
214 /*-----------------------------------------------------------------------
215 * External Bus Controller (EBC) Setup
216 *----------------------------------------------------------------------*/
218 /* Memory Bank 0 (Flash) initialization */
219 #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
220 EBC_BXAP_TWT_ENCODE(7) | \
221 EBC_BXAP_BCE_DISABLE | \
222 EBC_BXAP_BCT_2TRANS | \
223 EBC_BXAP_CSN_ENCODE(0) | \
224 EBC_BXAP_OEN_ENCODE(0) | \
225 EBC_BXAP_WBN_ENCODE(0) | \
226 EBC_BXAP_WBF_ENCODE(0) | \
227 EBC_BXAP_TH_ENCODE(0) | \
228 EBC_BXAP_RE_DISABLED | \
229 EBC_BXAP_SOR_DELAYED | \
230 EBC_BXAP_BEM_WRITEONLY | \
231 EBC_BXAP_PEN_DISABLED)
232 #define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
237 /* Memory Bank 1 (Xilinx System ACE controller) initialization */
238 #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
239 EBC_BXAP_TWT_ENCODE(4) | \
240 EBC_BXAP_BCE_DISABLE | \
241 EBC_BXAP_BCT_2TRANS | \
242 EBC_BXAP_CSN_ENCODE(0) | \
243 EBC_BXAP_OEN_ENCODE(0) | \
244 EBC_BXAP_WBN_ENCODE(0) | \
245 EBC_BXAP_WBF_ENCODE(0) | \
246 EBC_BXAP_TH_ENCODE(0) | \
247 EBC_BXAP_RE_DISABLED | \
248 EBC_BXAP_SOR_NONDELAYED | \
249 EBC_BXAP_BEM_WRITEONLY | \
250 EBC_BXAP_PEN_DISABLED)
251 #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE) | \
256 /*-------------------------------------------------------------------------
257 * Initialize EBC CONFIG -
258 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
259 * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
260 *-------------------------------------------------------------------------*/
261 #define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \
262 EBC_CFG_PTD_ENABLE | \
263 EBC_CFG_RTC_16PERCLK | \
264 EBC_CFG_ATC_PREVIOUS | \
265 EBC_CFG_DTC_PREVIOUS | \
266 EBC_CFG_CTC_PREVIOUS | \
267 EBC_CFG_OEO_PREVIOUS | \
268 EBC_CFG_EMC_DEFAULT | \
269 EBC_CFG_PME_DISABLE | \
272 /*-----------------------------------------------------------------------
274 *----------------------------------------------------------------------*/
275 #define CONFIG_SYS_GPIO_PCIE_PRESENT0 17
276 #define CONFIG_SYS_GPIO_PCIE_PRESENT1 21
277 #define CONFIG_SYS_GPIO_PCIE_PRESENT2 23
278 #define CONFIG_SYS_GPIO_RS232_FORCEOFF 30
280 #define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
281 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
282 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
283 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
284 #define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
285 #define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
286 #define CONFIG_SYS_GPIO_ODR 0
288 #endif /* __CONFIG_H */