3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33 #define CONFIG_MPC5200 1 /* especially an MPC5200 */
34 #define CONFIG_JUPITER 1 /* ... on Jupiter board */
37 * Valid values for CONFIG_SYS_TEXT_BASE are:
38 * 0xFFF00000 boot high (standard configuration)
39 * 0x00100000 boot from RAM (for testing only)
41 #ifndef CONFIG_SYS_TEXT_BASE
42 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
45 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
47 #define CONFIG_BOARD_EARLY_INIT_R 1
48 #define CONFIG_BOARD_EARLY_INIT_F 1
50 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
53 * Serial console configuration
55 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
56 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
57 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
61 * 0x40000000 - 0x4fffffff - PCI Memory
62 * 0x50000000 - 0x50ffffff - PCI IO Space
64 /*#define CONFIG_PCI */
66 #if defined(CONFIG_PCI)
67 #define CONFIG_PCI_PNP 1
68 #define CONFIG_PCI_SCAN_SHOW 1
69 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
71 #define CONFIG_PCI_MEM_BUS 0x40000000
72 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
73 #define CONFIG_PCI_MEM_SIZE 0x10000000
75 #define CONFIG_PCI_IO_BUS 0x50000000
76 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
77 #define CONFIG_PCI_IO_SIZE 0x01000000
80 #define CONFIG_SYS_XLB_PIPELINING 1
83 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
86 #define CONFIG_MAC_PARTITION
87 #define CONFIG_DOS_PARTITION
88 #define CONFIG_ISO_PARTITION
90 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
96 #define CONFIG_BOOTP_BOOTFILESIZE
97 #define CONFIG_BOOTP_BOOTPATH
98 #define CONFIG_BOOTP_GATEWAY
99 #define CONFIG_BOOTP_HOSTNAME
103 * Command line configuration.
105 #include <config_cmd_default.h>
107 #define CONFIG_CMD_NFS
108 #define CONFIG_CMD_SNTP
110 #if defined(CONFIG_PCI)
111 #define CODFIG_CMD_PCI
118 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
120 #define CONFIG_PREBOOT "echo;" \
121 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
124 #undef CONFIG_BOOTARGS
126 #define CONFIG_EXTRA_ENV_SETTINGS \
128 "nfsargs=setenv bootargs root=/dev/nfs rw " \
129 "nfsroot=${serverip}:${rootpath}\0" \
130 "ramargs=setenv bootargs root=/dev/ram rw\0" \
131 "addip=setenv bootargs ${bootargs} " \
132 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
133 ":${hostname}:${netdev}:off panic=1\0" \
134 "flash_nfs=run nfsargs addip addcons;" \
135 "bootm ${kernel_addr}\0" \
136 "flash_self=run ramargs addip;" \
137 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
138 "addcons=setenv bootargs ${bootargs} console=${contyp}," \
141 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
143 "rootpath=/opt/eldk/ppc_6xx\0" \
144 "bootfile=/tftpboot/jupiter/uImage\0" \
147 #define CONFIG_BOOTCOMMAND "run flash_self"
150 * IPB Bus clocking configuration.
152 #undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
155 /* pass open firmware flat tree */
156 #define CONFIG_OF_LIBFDT 1
157 #define CONFIG_OF_BOARD_SETUP 1
159 #define OF_CPU "PowerPC,5200@0"
160 #define OF_SOC "soc5200@f0000000"
161 #define OF_TBCLK (bd->bi_busfreq / 8)
162 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
169 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
170 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
172 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
173 #define CONFIG_SYS_I2C_SLAVE 0x7F
176 * EEPROM configuration
178 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
179 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
180 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
181 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
185 * Flash configuration
187 #define CONFIG_SYS_FLASH_BASE 0xFF000000
188 #define CONFIG_SYS_FLASH_SIZE 0x01000000
190 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
192 #define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + 0x40000) /* third sector */
194 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
195 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
197 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
199 #define CONFIG_FLASH_CFI_DRIVER
200 #define CONFIG_SYS_FLASH_CFI
201 #define CONFIG_SYS_FLASH_EMPTY_INFO
202 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
203 #define CONFIG_SYS_UPDATE_FLASH_SIZE 1
204 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
207 * Environment settings
209 #define CONFIG_ENV_IS_IN_FLASH 1
210 #define CONFIG_ENV_SIZE 0x20000
211 #define CONFIG_ENV_SECT_SIZE 0x20000
212 #define CONFIG_ENV_OVERWRITE 1
214 /* Address and size of Redundant Environment Sector */
215 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
216 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
221 #define CONFIG_SYS_MBAR 0xF0000000
222 #define CONFIG_SYS_SDRAM_BASE 0x00000000
223 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
225 /* Use SRAM until RAM will be available */
226 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
227 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
230 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
231 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
233 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
234 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
235 # define CONFIG_SYS_RAMBOOT 1
238 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
239 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
240 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
243 * Ethernet configuration
245 #define CONFIG_MPC5xxx_FEC 1
246 #define CONFIG_MPC5xxx_FEC_MII100
248 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
250 /* #define CONFIG_MPC5xxx_FEC_MII10 */
251 #define CONFIG_PHY_ADDR 0x00
256 #define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
259 * Miscellaneous configurable options
261 #define CONFIG_SYS_LONGHELP /* undef to save memory */
262 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
264 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
265 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
266 #if defined(CONFIG_CMD_KGDB)
267 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
269 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
271 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
272 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
273 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
275 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
276 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
277 #define CONFIG_SYS_ALT_MEMTEST 1
279 #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
281 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
283 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
284 #if defined(CONFIG_CMD_KGDB)
285 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
289 * Various low-level settings
291 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
292 #define CONFIG_SYS_HID0_FINAL HID0_ICE
294 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
295 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
296 #define CONFIG_SYS_BOOTCS_CFG 0x00047801
297 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
298 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
300 #define CONFIG_SYS_CS_BURST 0x00000000
301 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
303 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
305 #endif /* __CONFIG_H */