3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
12 * High Level Configuration Options
16 #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
17 #define CONFIG_JUPITER 1 /* ... on Jupiter board */
18 #define CONFIG_DISPLAY_BOARDINFO
21 * Valid values for CONFIG_SYS_TEXT_BASE are:
22 * 0xFFF00000 boot high (standard configuration)
23 * 0x00100000 boot from RAM (for testing only)
25 #ifndef CONFIG_SYS_TEXT_BASE
26 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
29 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
31 #define CONFIG_BOARD_EARLY_INIT_R 1
32 #define CONFIG_BOARD_EARLY_INIT_F 1
34 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
37 * Serial console configuration
39 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
40 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
41 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
45 * 0x40000000 - 0x4fffffff - PCI Memory
46 * 0x50000000 - 0x50ffffff - PCI IO Space
48 /*#define CONFIG_PCI */
50 #if defined(CONFIG_PCI)
51 #define CONFIG_PCI_PNP 1
52 #define CONFIG_PCI_SCAN_SHOW 1
53 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
55 #define CONFIG_PCI_MEM_BUS 0x40000000
56 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
57 #define CONFIG_PCI_MEM_SIZE 0x10000000
59 #define CONFIG_PCI_IO_BUS 0x50000000
60 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
61 #define CONFIG_PCI_IO_SIZE 0x01000000
64 #define CONFIG_SYS_XLB_PIPELINING 1
67 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
70 #define CONFIG_MAC_PARTITION
71 #define CONFIG_DOS_PARTITION
72 #define CONFIG_ISO_PARTITION
74 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
79 #define CONFIG_BOOTP_BOOTFILESIZE
80 #define CONFIG_BOOTP_BOOTPATH
81 #define CONFIG_BOOTP_GATEWAY
82 #define CONFIG_BOOTP_HOSTNAME
85 * Command line configuration.
88 #if defined(CONFIG_PCI)
89 #define CODFIG_CMD_PCI
95 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
97 #define CONFIG_PREBOOT "echo;" \
98 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
101 #undef CONFIG_BOOTARGS
103 #define CONFIG_EXTRA_ENV_SETTINGS \
105 "nfsargs=setenv bootargs root=/dev/nfs rw " \
106 "nfsroot=${serverip}:${rootpath}\0" \
107 "ramargs=setenv bootargs root=/dev/ram rw\0" \
108 "addip=setenv bootargs ${bootargs} " \
109 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
110 ":${hostname}:${netdev}:off panic=1\0" \
111 "flash_nfs=run nfsargs addip addcons;" \
112 "bootm ${kernel_addr}\0" \
113 "flash_self=run ramargs addip;" \
114 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
115 "addcons=setenv bootargs ${bootargs} console=${contyp}," \
118 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
120 "rootpath=/opt/eldk/ppc_6xx\0" \
121 "bootfile=/tftpboot/jupiter/uImage\0" \
124 #define CONFIG_BOOTCOMMAND "run flash_self"
127 * IPB Bus clocking configuration.
129 #undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
132 /* pass open firmware flat tree */
133 #define OF_CPU "PowerPC,5200@0"
134 #define OF_SOC "soc5200@f0000000"
135 #define OF_TBCLK (bd->bi_busfreq / 8)
136 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
143 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
144 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
146 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
147 #define CONFIG_SYS_I2C_SLAVE 0x7F
150 * EEPROM configuration
152 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
153 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
154 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
155 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
159 * Flash configuration
161 #define CONFIG_SYS_FLASH_BASE 0xFF000000
162 #define CONFIG_SYS_FLASH_SIZE 0x01000000
164 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
166 #define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + 0x40000) /* third sector */
168 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
169 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
171 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
173 #define CONFIG_FLASH_CFI_DRIVER
174 #define CONFIG_SYS_FLASH_CFI
175 #define CONFIG_SYS_FLASH_EMPTY_INFO
176 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
177 #define CONFIG_SYS_UPDATE_FLASH_SIZE 1
178 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
181 * Environment settings
183 #define CONFIG_ENV_IS_IN_FLASH 1
184 #define CONFIG_ENV_SIZE 0x20000
185 #define CONFIG_ENV_SECT_SIZE 0x20000
186 #define CONFIG_ENV_OVERWRITE 1
188 /* Address and size of Redundant Environment Sector */
189 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
190 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
195 #define CONFIG_SYS_MBAR 0xF0000000
196 #define CONFIG_SYS_SDRAM_BASE 0x00000000
197 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
199 /* Use SRAM until RAM will be available */
200 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
201 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
203 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
204 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
206 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
207 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
208 # define CONFIG_SYS_RAMBOOT 1
211 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
212 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
213 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
216 * Ethernet configuration
218 #define CONFIG_MPC5xxx_FEC 1
219 #define CONFIG_MPC5xxx_FEC_MII100
221 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
223 /* #define CONFIG_MPC5xxx_FEC_MII10 */
224 #define CONFIG_PHY_ADDR 0x00
229 #define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
232 * Miscellaneous configurable options
234 #define CONFIG_SYS_LONGHELP /* undef to save memory */
236 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
237 #if defined(CONFIG_CMD_KGDB)
238 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
240 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
242 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
243 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
244 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
246 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
247 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
248 #define CONFIG_SYS_ALT_MEMTEST 1
250 #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
252 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
253 #if defined(CONFIG_CMD_KGDB)
254 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
258 * Various low-level settings
260 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
261 #define CONFIG_SYS_HID0_FINAL HID0_ICE
263 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
264 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
265 #define CONFIG_SYS_BOOTCS_CFG 0x00047801
266 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
267 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
269 #define CONFIG_SYS_CS_BURST 0x00000000
270 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
272 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
274 #endif /* __CONFIG_H */