2 * (C) Copyright 2005-2006
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
6 * Martijn de Gouw, Prodrive B.V., martijn.de.gouw@prodrive.nl
8 * Configuation settings for the IXDPG425 board.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * High Level Configuration Options
36 #define CONFIG_IXP425 1 /* This is an IXP425 CPU */
37 #define CONFIG_IXDPG425 1 /* on an IXDPG425 Board */
39 #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
40 #define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
45 #define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */
46 #define CONFIG_NET_MULTI 1
47 #define CONFIG_PHY_ADDR 5 /* NPE0 PHY address */
48 #define CONFIG_HAS_ETH1
49 #define CONFIG_PHY1_ADDR 4 /* NPE1 PHY address */
50 #define CONFIG_MII 1 /* MII PHY management */
51 #define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
54 * Misc configuration options
56 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
57 #define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */
59 #define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
60 #define CFG_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */
62 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
63 #define CONFIG_SETUP_MEMORY_TAGS 1
64 #define CONFIG_INITRD_TAG 1
67 * Size of malloc() pool
69 #define CFG_MALLOC_LEN (256 << 10)
70 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
72 /* allow to overwrite serial and ethaddr */
73 #define CONFIG_ENV_OVERWRITE
75 #define CONFIG_BAUDRATE 115200
76 #define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
80 * Command line configuration.
82 #include <config_cmd_default.h>
84 #define CONFIG_CMD_DHCP
85 #define CONFIG_CMD_ELF
86 #define CONFIG_CMD_NET
87 #define CONFIG_CMD_MII
88 #define CONFIG_CMD_PING
91 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
92 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
95 * Miscellaneous configurable options
97 #define CFG_LONGHELP /* undef to save memory */
98 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
99 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
100 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
101 #define CFG_MAXARGS 16 /* max number of command args */
102 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
104 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
105 #define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
106 #define CFG_LOAD_ADDR 0x00010000 /* default load address */
108 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
109 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
111 /* valid baudrates */
112 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
117 * The stack sizes are set up in start.S using the settings below
119 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
120 #ifdef CONFIG_USE_IRQ
121 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
122 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
125 /***************************************************************
126 * Platform/Board specific defines start here.
127 ***************************************************************/
129 /*-----------------------------------------------------------------------
130 * Default configuration (environment varibles...)
131 *----------------------------------------------------------------------*/
132 #define CONFIG_PREBOOT "echo;" \
133 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
136 #undef CONFIG_BOOTARGS
138 #define CONFIG_EXTRA_ENV_SETTINGS \
140 "hostname=ixdpg425\0" \
141 "nfsargs=setenv bootargs root=/dev/nfs rw " \
142 "nfsroot=${serverip}:${rootpath}\0" \
143 "ramargs=setenv bootargs root=/dev/ram rw\0" \
144 "addip=setenv bootargs ${bootargs} " \
145 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
146 ":${hostname}:${netdev}:off panic=1\0" \
147 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
148 "flash_nfs=run nfsargs addip addtty;" \
149 "bootm ${kernel_addr}\0" \
150 "flash_self=run ramargs addip addtty;" \
151 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
152 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
154 "rootpath=/opt/eldk/arm\0" \
155 "bootfile=/tftpboot/ixdpg425/uImage\0" \
156 "kernel_addr=50080000\0" \
157 "ramdisk_addr=50200000\0" \
158 "load=tftp 100000 /tftpboot/ixdpg425/u-boot.bin\0" \
159 "update=protect off 50000000 5003ffff;era 50000000 5003ffff;" \
160 "cp.b 100000 50000000 40000;" \
161 "setenv filesize;saveenv\0" \
162 "upd=run load;run update\0" \
164 #define CONFIG_BOOTCOMMAND "run net_nfs"
167 * Physical Memory Map
169 #define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */
170 #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
171 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
173 #define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */
174 #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
175 #define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
176 #define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
178 #define CFG_DRAM_BASE 0x00000000
179 #define CFG_DRAM_SIZE 0x01000000
181 #define CFG_FLASH_BASE PHYS_FLASH_1
182 #define CFG_MONITOR_BASE CFG_FLASH_BASE
183 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
186 * Expansion bus settings
188 #define CFG_EXP_CS0 0xbcd23c42
193 #define CFG_SDR_CONFIG 0x18
194 #define CFG_SDR_MODE_CONFIG 0x1
195 #define CFG_SDRAM_REFRESH_CNT 0x81a
198 * FLASH and environment organization
200 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
201 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
203 #define CFG_FLASH_CFI /* The flash is CFI compatible */
204 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
205 #define CFG_ENV_IS_IN_FLASH 1
207 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
208 #define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
210 #define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
212 #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
214 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
215 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
217 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
219 #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
220 #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
221 #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
223 /* Address and size of Redundant Environment Sector */
224 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
225 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
230 #define CFG_GPIO_PCI_INTA_N 6
231 #define CFG_GPIO_PCI_INTB_N 7
232 #define CFG_GPIO_SWITCH_RESET_N 8
233 #define CFG_GPIO_SLIC_RESET_N 13
234 #define CFG_GPIO_PCI_CLK 14
235 #define CFG_GPIO_EXTBUS_CLK 15
238 * Cache Configuration
240 #define CFG_CACHELINE_SIZE 32
242 #endif /* __CONFIG_H */