include/configs/ipek01.h

   1 /*
   2  * (C) Copyright 2006
   3  * MicroSys GmbH
   4  *
   5  * (C) Copyright 2009
   6  * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  */
  17
  18 #define CONFIG_MPC5200
  19 #define CONFIG_MPX5200          1       /* MPX5200 board */
  20 #define CONFIG_MPC5200_DDR      1       /* use DDR RAM */
  21 #define CONFIG_IPEK01                   /* Motherboard is ipek01 */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xfc000000
  24
  25 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33MHz */
  26
  27 #define CONFIG_MISC_INIT_R
  28
  29 #define CONFIG_SYS_CACHELINE_SIZE       32 /* For MPC5xxx CPUs */
  30 #ifdef CONFIG_CMD_KGDB
  31 #define CONFIG_SYS_CACHELINE_SHIFT      5  /* log base 2 of the above value */
  32 #endif
  33
  34 /*
  35  * Serial console configuration
  36  */
  37 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  38 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  39
  40 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
  41
  42 /*
  43  * Video configuration for LIME GDC
  44  */
  45 #ifdef CONFIG_VIDEO
  46 #define CONFIG_VIDEO_MB862xx
  47 #define CONFIG_VIDEO_MB862xx_ACCEL
  48 #define VIDEO_FB_16BPP_WORD_SWAP
  49 #define CONFIG_VIDEO_LOGO
  50 #define CONFIG_VIDEO_BMP_LOGO
  51 #define CONFIG_SPLASH_SCREEN
  52 #define CONFIG_VIDEO_BMP_GZIP
  53 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)       /* decompressed img */
  54 /* Lime clock frequency */
  55 #define CONFIG_SYS_MB862xx_CCF  0x90000 /* geo 166MHz other 133MHz */
  56 /* SDRAM parameter */
  57 #define CONFIG_SYS_MB862xx_MMR  0x41c767e3
  58 #endif
  59
  60 /*
  61  * PCI Mapping:
  62  * 0x40000000 - 0x4fffffff - PCI Memory
  63  * 0x50000000 - 0x50ffffff - PCI IO Space
  64  */
  65 #define CONFIG_PCI_SCAN_SHOW    1
  66
  67 #define CONFIG_PCI_MEM_BUS      0x40000000
  68 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  69 #define CONFIG_PCI_MEM_SIZE     0x10000000
  70
  71 #define CONFIG_PCI_IO_BUS       0x50000000
  72 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  73 #define CONFIG_PCI_IO_SIZE      0x01000000
  74
  75 #define CONFIG_MII              1
  76 #define CONFIG_EEPRO100         1
  77 #define CONFIG_SYS_RX_ETH_BUFFER        8  /* use 8 rx buffer on eepro100  */
  78
  79 /* USB */
  80 #define CONFIG_USB_OHCI_NEW
  81 #define CONFIG_SYS_OHCI_BE_CONTROLLER
  82
  83 #define CONFIG_SYS_USB_OHCI_CPU_INIT
  84 #define CONFIG_SYS_USB_OHCI_REGS_BASE           MPC5XXX_USB
  85 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "mpc5200"
  86 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
  87
  88 /*
  89  * Command line configuration.
  90  */
  91 #define CONFIG_CMD_IDE          /* IDE harddisk support */
  92 #define CONFIG_CMD_IRQ          /* irqinfo */
  93 #define CONFIG_CMD_PCI          /* pciinfo */
  94
  95 #define CONFIG_SYS_LOWBOOT      1
  96
  97 /*
  98  * Autobooting
  99  */
 100
 101 #define CONFIG_PREBOOT  "echo;" \
 102         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 103         "echo"
 104
 105 #undef  CONFIG_BOOTARGS
 106
 107 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 108         "netdev=eth0\0"                                                 \
 109         "consoledev=ttyPSC0\0"                                          \
 110         "hostname=ipek01\0"                                             \
 111         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 112                 "nfsroot=${serverip}:${rootpath}\0"                     \
 113         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 114         "addip=setenv bootargs ${bootargs} "                            \
 115                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 116                 ":${hostname}:${netdev}:off panic=1\0"                  \
 117         "addtty=setenv bootargs ${bootargs} "                           \
 118                 "console=${consoledev},${baudrate}\0"                   \
 119         "flash_nfs=run nfsargs addip addtty;"                           \
 120                 "bootm ${kernel_addr} - ${fdtaddr}\0"                   \
 121         "flash_self=run ramargs addip addtty;"                          \
 122                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0"     \
 123         "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};"  \
 124                 "run nfsargs addip addtty;"                             \
 125                  "bootm ${loadaddr} - ${fdtaddr}\0"                     \
 126         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 127         "bootfile=ipek01/uImage\0"                                      \
 128         "load=tftp 100000 ipek01/u-boot.bin\0"                          \
 129         "update=protect off FC000000 +60000; era FC000000 +60000; "     \
 130                 "cp.b 100000 FC000000 ${filesize}\0"                    \
 131         "upd=run load;run update\0"                                     \
 132         "fdtaddr=800000\0"                                              \
 133         "loadaddr=400000\0"                                             \
 134         "fdtfile=ipek01/ipek01.dtb\0"                                   \
 135         ""
 136
 137 #define CONFIG_BOOTCOMMAND      "run flash_self"
 138
 139 /*
 140  * IPB Bus clocking configuration.
 141  */
 142 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* for 133MHz */
 143 /* PCI clock must be 33, because board will not boot */
 144 #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2     /* for 66MHz */
 145
 146 /*
 147  * Open firmware flat tree support
 148  */
 149 #define OF_CPU                  "PowerPC,5200@0"
 150 #define OF_SOC                  "soc5200@f0000000"
 151 #define OF_TBCLK                (bd->bi_busfreq / 4)
 152
 153 /*
 154  * I2C configuration
 155  */
 156 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 157 #define CONFIG_SYS_I2C_MODULE   2       /* Select I2C module #1 or #2 */
 158
 159 #define CONFIG_SYS_I2C_SPEED    100000  /* 100 kHz */
 160 #define CONFIG_SYS_I2C_SLAVE    0x7F
 161
 162 /*
 163  * EEPROM configuration
 164  */
 165 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 166 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 167 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 168 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 169
 170 /*
 171  * RTC configuration
 172  */
 173 #define CONFIG_RTC_PCF8563
 174 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 175
 176 #define CONFIG_SYS_FLASH_BASE           0xFC000000
 177 #define CONFIG_SYS_FLASH_SIZE           0x01000000
 178 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + \
 179                                          CONFIG_SYS_MONITOR_LEN)
 180
 181 #define CONFIG_SYS_MAX_FLASH_BANKS      1    /* max num of memory banks */
 182 #define CONFIG_SYS_MAX_FLASH_SECT       256  /* max num of sects on one chip */
 183 #define CONFIG_SYS_FLASH_PROTECTION  /* "Real" (hardware) sectors protection */
 184
 185 /* use CFI flash driver */
 186 #define CONFIG_FLASH_CFI_DRIVER
 187 #define CONFIG_SYS_FLASH_CFI
 188 #define CONFIG_SYS_FLASH_EMPTY_INFO
 189 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
 190
 191 /*
 192  * Environment settings
 193  */
 194 #define CONFIG_ENV_IS_IN_FLASH          1
 195 #define CONFIG_ENV_SIZE                 0x10000
 196 #define CONFIG_ENV_SECT_SIZE            0x20000
 197 #define CONFIG_ENV_OVERWRITE            1
 198 #define CONFIG_ENV_ADDR_REDUND          (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 199 #define CONFIG_ENV_SIZE_REDUND          CONFIG_ENV_SIZE
 200
 201 /*
 202  * Memory map
 203  */
 204 #define CONFIG_SYS_MBAR                 0xf0000000
 205 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 206 #define CONFIG_SYS_DEFAULT_MBAR         0x80000000
 207 #define CONFIG_SYS_SRAM_BASE            0xF1000000
 208 #define CONFIG_SYS_SRAM_SIZE            0x00200000
 209 #define CONFIG_SYS_LIME_BASE            0xE4000000
 210 #define CONFIG_SYS_LIME_SIZE            0x04000000
 211 #define CONFIG_SYS_FPGA_BASE            0xC0000000
 212 #define CONFIG_SYS_FPGA_SIZE            0x10000000
 213 #define CONFIG_SYS_MPEG_BASE            0xe2000000
 214 #define CONFIG_SYS_MPEG_SIZE            0x01000000
 215 #define CONFIG_SYS_CF_BASE              0xe1000000
 216 #define CONFIG_SYS_CF_SIZE              0x01000000
 217
 218 /* Use SRAM until RAM will be available */
 219 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 220 /* End of used area in DPRAM */
 221 #define CONFIG_SYS_INIT_RAM_SIZE                MPC5XXX_SRAM_SIZE
 222
 223 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 224                                          GENERATED_GBL_DATA_SIZE)
 225 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 226
 227 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 228 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 229 #   define CONFIG_SYS_RAMBOOT           1
 230 #endif
 231
 232 #define CONFIG_SYS_MONITOR_LEN  (384 << 10)  /* Reserve 384 kB for Monitor */
 233 #define CONFIG_SYS_MALLOC_LEN   (4 << 20)    /* Reserve 128 kB for malloc() */
 234 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)    /* Initial Memory map for Linux */
 235
 236 /*
 237  * Ethernet configuration
 238  */
 239 #define CONFIG_MPC5xxx_FEC              1
 240 #define CONFIG_MPC5xxx_FEC_MII100
 241 #define CONFIG_PHY_ADDR                 0x00
 242
 243 /*
 244  * GPIO configuration
 245  */
 246 #define CONFIG_SYS_GPS_PORT_CONFIG      0x1d556624
 247
 248 /*
 249  * Miscellaneous configurable options
 250  */
 251 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 252 #ifdef CONFIG_CMD_KGDB
 253 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
 254 #else
 255 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 256 #endif
 257 /* Print Buffer Size */
 258 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 259                                          sizeof(CONFIG_SYS_PROMPT) + 16)
 260 /* max number of command args */
 261 #define CONFIG_SYS_MAXARGS              16
 262 /* Boot Argument Buffer Size */
 263 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 264
 265 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 266 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1...15 MB in DRAM */
 267
 268 #define CONFIG_SYS_LOAD_ADDR            0x100000 /* default load address */
 269
 270 /*
 271  * Various low-level settings
 272  */
 273 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 274 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 275
 276 #define CONFIG_SYS_BOOTCS_START         CONFIG_SYS_FLASH_BASE
 277 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 278 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 279 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 280 #define CONFIG_SYS_CS1_START            CONFIG_SYS_SRAM_BASE
 281 #define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_SRAM_SIZE
 282 #define CONFIG_SYS_CS3_START            CONFIG_SYS_LIME_BASE
 283 #define CONFIG_SYS_CS3_SIZE             CONFIG_SYS_LIME_SIZE
 284 #define CONFIG_SYS_CS6_START            CONFIG_SYS_FPGA_BASE
 285 #define CONFIG_SYS_CS6_SIZE             CONFIG_SYS_FPGA_SIZE
 286 #define CONFIG_SYS_CS5_START            CONFIG_SYS_CF_BASE
 287 #define CONFIG_SYS_CS5_SIZE             CONFIG_SYS_CF_SIZE
 288 #define CONFIG_SYS_CS7_START            CONFIG_SYS_MPEG_BASE
 289 #define CONFIG_SYS_CS7_SIZE             CONFIG_SYS_MPEG_SIZE
 290
 291 #ifdef CONFIG_SYS_PCISPEED_66
 292 #define CONFIG_SYS_BOOTCS_CFG           0x0006F900
 293 #define CONFIG_SYS_CS1_CFG              0x0004FB00
 294 #define CONFIG_SYS_CS2_CFG              0x0006F900
 295 #else
 296 #define CONFIG_SYS_BOOTCS_CFG           0x0002F900
 297 #define CONFIG_SYS_CS1_CFG              0x0001FB00
 298 #define CONFIG_SYS_CS2_CFG              0x0002F90C
 299 #endif
 300
 301 /*
 302  * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
 303  * waitstates, writeswap and readswap enabled
 304  */
 305 #define CONFIG_SYS_CS3_CFG              0x00FFFB0C
 306 #define CONFIG_SYS_CS6_CFG              0x00FFFB0C
 307 #define CONFIG_SYS_CS7_CFG              0x4040751C
 308
 309 #define CONFIG_SYS_CS_BURST             0x00000000
 310 #define CONFIG_SYS_CS_DEADCYCLE         0x33330000
 311
 312 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 313
 314 /*-----------------------------------------------------------------------
 315  * USB stuff
 316  *-----------------------------------------------------------------------
 317  */
 318 #define CONFIG_USB_CLOCK                0x0001BBBB
 319 #define CONFIG_USB_CONFIG               0x00005000
 320
 321 /*-----------------------------------------------------------------------
 322  * IDE/ATA stuff Supports IDE harddisk
 323  *-----------------------------------------------------------------------
 324  */
 325 #define CONFIG_IDE_PREINIT
 326
 327 #define CONFIG_SYS_IDE_MAXBUS           1 /* max. 1 IDE bus */
 328 #define CONFIG_SYS_IDE_MAXDEVICE        2 /* max. 2 drives per IDE bus */
 329
 330 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 331
 332 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 333
 334 /* Offset for data I/O */
 335 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 336
 337 /* Offset for normal register accesses */
 338 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 339
 340 /* Offset for alternate registers */
 341 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 342
 343 /* Interval between registers */
 344 #define CONFIG_SYS_ATA_STRIDE           4
 345
 346 #endif /* __CONFIG_H */