Merge git://git.denx.de/u-boot-dm
[platform/kernel/u-boot.git] / include / configs / ipam390.h
1 /*
2  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
3  * Based on:
4  * U-Boot:include/configs/da850evm.h
5  *
6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7  *
8  * Based on davinci_dvevm.h. Original Copyrights follow:
9  *
10  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
11  *
12  * SPDX-License-Identifier:     GPL-2.0+
13  */
14
15 #ifndef __CONFIG_H
16 #define __CONFIG_H
17
18 /*
19  * Board
20  */
21 #define CONFIG_DRIVER_TI_EMAC
22 #define CONFIG_BARIX_IPAM390
23
24 /*
25  * SoC Configuration
26  */
27 #define CONFIG_MACH_DAVINCI_DA850_EVM
28 #define CONFIG_SOC_DA8XX                /* TI DA8xx SoC */
29 #define CONFIG_SOC_DA850                /* TI DA850 SoC */
30 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
31 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
32 #define CONFIG_SYS_OSCIN_FREQ           24000000
33 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
34 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
35 #define CONFIG_SYS_DA850_PLL_INIT
36 #define CONFIG_SYS_DA850_DDR_INIT
37 #define CONFIG_SYS_TEXT_BASE            0xc1080000
38
39 /*
40  * Memory Info
41  */
42 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
43 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
44 #define PHYS_SDRAM_1_SIZE       (128 << 20) /* SDRAM size 128MB */
45 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
46
47 /* memtest start addr */
48 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
49
50 /* memtest will be run on 16MB */
51 #define CONFIG_SYS_MEMTEST_END  (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024)
52
53 #define CONFIG_NR_DRAM_BANKS    1 /* we have 1 bank of DRAM */
54
55 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
56         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
57         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
58         DAVINCI_SYSCFG_SUSPSRC_UART0 |          \
59         DAVINCI_SYSCFG_SUSPSRC_EMAC)
60
61 /*
62  * PLL configuration
63  */
64 #define CONFIG_SYS_DV_CLKMODE          0
65 #define CONFIG_SYS_DA850_PLL0_POSTDIV  1
66 #define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
67 #define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
68 #define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
69 #define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
70 #define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
71 #define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
72 #define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
73
74 #define CONFIG_SYS_DA850_PLL1_POSTDIV  1
75 #define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
76 #define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
77 #define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002
78
79 #define CONFIG_SYS_DA850_PLL0_PLLM     24
80 #define CONFIG_SYS_DA850_PLL1_PLLM     24
81
82 /*
83  * DDR2 memory configuration
84  */
85 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
86                                         DV_DDR_PHY_EXT_STRBEN | \
87                                         (0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT))
88 #define CONFIG_SYS_DA850_DDR2_SDRCR     0x00000498
89
90 #define CONFIG_SYS_DA850_DDR2_SDBCR2    0x00000004
91 #define CONFIG_SYS_DA850_DDR2_PBBPR     0x00000020
92
93
94 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
95         (13 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
96         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
97         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
98         (2 << DV_DDR_SDTMR1_WR_SHIFT) |         \
99         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
100         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
101         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
102         (1 << DV_DDR_SDTMR1_WTR_SHIFT))
103
104 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
105         (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
106         (2 << DV_DDR_SDTMR2_XP_SHIFT) |         \
107         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
108         (14 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
109         (0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) |    \
110         (1 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
111         (2 << DV_DDR_SDTMR2_CKE_SHIFT))
112
113 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
114         (1 << DV_DDR_SDCR_DDR2EN_SHIFT) |       \
115         (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) |    \
116         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
117         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
118         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
119         (2 << DV_DDR_SDCR_CL_SHIFT) |   \
120         (3 << DV_DDR_SDCR_IBANK_SHIFT) |        \
121         (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
122
123 #define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
124                                 DAVINCI_ABCR_WSTROBE(2) | \
125                                 DAVINCI_ABCR_WHOLD(0)   | \
126                                 DAVINCI_ABCR_RSETUP(1)  | \
127                                 DAVINCI_ABCR_RSTROBE(2) | \
128                                 DAVINCI_ABCR_RHOLD(1)   | \
129                                 DAVINCI_ABCR_TA(0)      | \
130                                 DAVINCI_ABCR_ASIZE_8BIT)
131
132
133 /*
134  * Serial Driver info
135  */
136 #define CONFIG_SYS_NS16550
137 #define CONFIG_SYS_NS16550_SERIAL
138 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
139 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
140 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
141 #define CONFIG_CONS_INDEX       1               /* use UART0 for console */
142 #define CONFIG_BAUDRATE         115200          /* Default baud rate */
143
144 /*
145  * Flash & Environment
146  */
147 #define CONFIG_NAND_DAVINCI
148 #define CONFIG_SYS_NO_FLASH
149 #define CONFIG_ENV_IS_IN_NAND           /* U-Boot env in NAND Flash  */
150 #define CONFIG_ENV_OFFSET               0x0 /* Block 0--not used by bootcode */
151 #define CONFIG_ENV_SIZE                 (128 << 10)
152 #define CONFIG_SYS_NAND_USE_FLASH_BBT
153 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
154 #define CONFIG_SYS_NAND_PAGE_2K
155 #define CONFIG_SYS_NAND_CS              3
156 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
157 #define CONFIG_SYS_NAND_MASK_CLE                0x10
158 #define CONFIG_SYS_NAND_MASK_ALE                0x8
159 #undef CONFIG_SYS_NAND_HW_ECC
160 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
161 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
162 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
163 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
164 #define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)
165 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
166 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
167 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x120000
168 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
169 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
170 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
171                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
172                                         CONFIG_SYS_MALLOC_LEN -       \
173                                         GENERATED_GBL_DATA_SIZE)
174 #define CONFIG_SYS_NAND_ECCPOS          {                               \
175                         6,   7,  8,  9, 10,     11, 12, 13, 14, 15,     \
176                         22, 23, 24, 25, 26,     27, 28, 29, 30, 31,     \
177                         38, 39, 40, 41, 42,     43, 44, 45, 46, 47,     \
178                         54, 55, 56, 57, 58,     59, 60, 61, 62, 63}
179 #define CONFIG_SYS_NAND_PAGE_COUNT      64
180 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
181 #define CONFIG_SYS_NAND_ECCSIZE         512
182 #define CONFIG_SYS_NAND_ECCBYTES        10
183 #define CONFIG_SYS_NAND_OOBSIZE         64
184 #define CONFIG_SPL_NAND_SUPPORT
185 #define CONFIG_SPL_NAND_BASE
186 #define CONFIG_SPL_NAND_DRIVERS
187 #define CONFIG_SPL_NAND_ECC
188 #define CONFIG_SPL_NAND_SIMPLE
189 #define CONFIG_SPL_NAND_LOAD
190
191 /*
192  * Network & Ethernet Configuration
193  */
194 #ifdef CONFIG_DRIVER_TI_EMAC
195 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
196 #define CONFIG_BOOTP_DEFAULT
197 #define CONFIG_BOOTP_DNS
198 #define CONFIG_BOOTP_DNS2
199 #define CONFIG_BOOTP_SEND_HOSTNAME
200 #define CONFIG_NET_RETRY_COUNT  10
201 #endif
202
203 /*
204  * U-Boot general configuration
205  */
206 #define CONFIG_MISC_INIT_R
207 #define CONFIG_BOARD_EARLY_INIT_F
208 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
209 #define CONFIG_SYS_PROMPT       "U-Boot > " /* Command Prompt */
210 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
211 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
212 #define CONFIG_SYS_MAXARGS      16 /* max number of command args */
213 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
214 #define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
215 #define CONFIG_VERSION_VARIABLE
216 #define CONFIG_AUTO_COMPLETE
217 #define CONFIG_SYS_HUSH_PARSER
218 #define CONFIG_CMDLINE_EDITING
219 #define CONFIG_SYS_LONGHELP
220 #define CONFIG_CRC32_VERIFY
221 #define CONFIG_MX_CYCLIC
222
223 /*
224  * Linux Information
225  */
226 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
227 #define CONFIG_HWCONFIG         /* enable hwconfig */
228 #define CONFIG_CMDLINE_TAG
229 #define CONFIG_REVISION_TAG
230 #define CONFIG_SETUP_MEMORY_TAGS
231 #define CONFIG_BOOTDELAY        2
232 #define CONFIG_EXTRA_ENV_SETTINGS \
233         "defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \
234                 "root=/dev/mtdblock5 rw noinitrd " \
235                 "rootfstype=jffs2 noinitrd\0" \
236         "hwconfig=dsp:wake=yes\0" \
237         "bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \
238         "bootfile=uImage\0" \
239         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"      \
240         "mtddevname=uboot-env\0" \
241         "mtddevnum=0\0" \
242         "mtdids=" MTDIDS_DEFAULT "\0"                           \
243         "mtdparts=" MTDPARTS_DEFAULT "\0"                       \
244         "u-boot=/tftpboot/ipam390/u-boot.ais\0"                 \
245         "upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \
246                 "nand write c0000000 20000 ${filesize}\0"       \
247         "setbootparms=nand read c0100000 200000 400000;"        \
248                 "run defbootargs addmtd;"                       \
249                 "spl export atags c0100000;"                    \
250                 "nand erase.part bootparms;"                    \
251                 "nand write c0000100 180000 20000\0"            \
252         "\0"
253
254 /*
255  * U-Boot commands
256  */
257 #include <config_cmd_default.h>
258 #define CONFIG_CMD_ENV
259 #define CONFIG_CMD_ASKENV
260 #define CONFIG_CMD_DHCP
261 #define CONFIG_CMD_DIAG
262 #define CONFIG_CMD_MII
263 #define CONFIG_CMD_PING
264 #define CONFIG_CMD_SAVES
265 #define CONFIG_CMD_MEMORY
266
267 #ifdef CONFIG_CMD_BDI
268 #define CONFIG_CLOCKS
269 #endif
270
271 #ifndef CONFIG_DRIVER_TI_EMAC
272 #undef CONFIG_CMD_NET
273 #undef CONFIG_CMD_DHCP
274 #undef CONFIG_CMD_MII
275 #undef CONFIG_CMD_PING
276 #endif
277
278 #define CONFIG_CMD_NAND
279 #define CONFIG_CMD_NAND_TRIMFFS
280
281 #define CONFIG_CMD_MTDPARTS
282 #define CONFIG_MTD_DEVICE
283 #define CONFIG_MTD_PARTITIONS
284 #define CONFIG_LZO
285 #define CONFIG_RBTREE
286 #define CONFIG_CMD_UBI
287 #define CONFIG_CMD_UBIFS
288
289 #define MTDIDS_NAME_STR         "davinci_nand.0"
290 #define MTDIDS_DEFAULT          "nand0=" MTDIDS_NAME_STR
291 #define MTDPARTS_DEFAULT        "mtdparts=" MTDIDS_NAME_STR ":" \
292                                         "128k(u-boot-env),"     \
293                                         "1408k(u-boot),"        \
294                                         "128k(bootparms),"      \
295                                         "384k(factory-info),"   \
296                                         "4M(kernel),"   \
297                                         "-(rootfs)"
298
299 /* defines for SPL */
300 #define CONFIG_SPL_FRAMEWORK
301 #define CONFIG_SPL_BOARD_INIT
302 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
303                                                 CONFIG_SYS_MALLOC_LEN)
304 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
305 #define CONFIG_SPL_SERIAL_SUPPORT
306 #define CONFIG_SPL_LIBCOMMON_SUPPORT
307 #define CONFIG_SPL_LIBGENERIC_SUPPORT
308 #define CONFIG_SPL_LDSCRIPT     "board/$(BOARDDIR)/u-boot-spl-ipam390.lds"
309 #define CONFIG_SPL_STACK        0x8001ff00
310 #define CONFIG_SPL_TEXT_BASE    0x80000000
311 #define CONFIG_SPL_MAX_SIZE     0x20000
312 #define CONFIG_SPL_MAX_FOOTPRINT        32768
313
314 /* additions for new relocation code, must added to all boards */
315 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
316
317 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
318                                         GENERATED_GBL_DATA_SIZE)
319
320 /* add FALCON boot mode */
321 #define CONFIG_CMD_SPL
322 #define CONFIG_SPL_OS_BOOT
323 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
324 #define CONFIG_SYS_SPL_ARGS_ADDR        LINUX_BOOT_PARAM_ADDR
325 #define CONFIG_CMD_SPL_NAND_OFS         0x00180000
326 #define CONFIG_CMD_SPL_WRITE_SIZE       0x400
327
328 /* GPIO support */
329 #define CONFIG_SPL_GPIO_SUPPORT
330 #define CONFIG_DA8XX_GPIO
331 #define CONFIG_IPAM390_GPIO_BOOTMODE    ((16 * 7) + 14)
332
333 #define CONFIG_SHOW_BOOT_PROGRESS
334 #define CONFIG_IPAM390_GPIO_LED_RED     ((16 * 7) + 11)
335 #define CONFIG_IPAM390_GPIO_LED_GREEN   ((16 * 7) + 12)
336
337 #endif /* __CONFIG_H */